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x86_64: implement prefetch
This commit is contained in:
Jacob Young
parent
82eedf56d7
commit
ff74127526
@ -2484,7 +2484,6 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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.reduce => try cg.airReduce(inst),
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.reduce_optimized => try cg.airReduce(inst),
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.aggregate_init => try cg.airAggregateInit(inst),
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.prefetch => try cg.airPrefetch(inst),
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// zig fmt: on
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.arg => if (cg.debug_output != .none) {
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@ -76418,6 +76417,33 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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}, cg);
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try res.finish(inst, &.{extra.init}, &ops, cg);
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},
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.prefetch => {
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const prefetch = air_datas[@intFromEnum(inst)].prefetch;
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var ops = try cg.tempsFromOperands(inst, .{prefetch.ptr});
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switch (prefetch.cache) {
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.instruction => {}, // prefetchi requires rip-relative addressing, which is currently non-trivial to emit from an arbitrary ptr value
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.data => if (prefetch.rw == .write and prefetch.locality <= 2 and cg.hasFeature(.prefetchwt1)) {
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try ops[0].toSlicePtr(cg);
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while (try ops[0].toLea(cg)) {}
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try cg.asmMemory(.{ ._wt1, .prefetch }, try ops[0].tracking(cg).short.deref().mem(cg, .{ .size = .byte }));
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} else if (prefetch.rw == .write and cg.hasFeature(.prfchw)) {
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try ops[0].toSlicePtr(cg);
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while (try ops[0].toLea(cg)) {}
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try cg.asmMemory(.{ ._w, .prefetch }, try ops[0].tracking(cg).short.deref().mem(cg, .{ .size = .byte }));
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} else if (cg.hasFeature(.sse) or cg.hasFeature(.prfchw) or cg.hasFeature(.prefetchi) or cg.hasFeature(.prefetchwt1)) {
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try ops[0].toSlicePtr(cg);
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while (try ops[0].toLea(cg)) {}
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switch (prefetch.locality) {
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0 => try cg.asmMemory(.{ ._nta, .prefetch }, try ops[0].tracking(cg).short.deref().mem(cg, .{ .size = .byte })),
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1 => try cg.asmMemory(.{ ._t2, .prefetch }, try ops[0].tracking(cg).short.deref().mem(cg, .{ .size = .byte })),
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2 => try cg.asmMemory(.{ ._t1, .prefetch }, try ops[0].tracking(cg).short.deref().mem(cg, .{ .size = .byte })),
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3 => try cg.asmMemory(.{ ._t0, .prefetch }, try ops[0].tracking(cg).short.deref().mem(cg, .{ .size = .byte })),
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}
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},
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}
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const res = try cg.tempInit(.void, .none);
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try res.finish(inst, &.{prefetch.ptr}, &ops, cg);
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},
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.mul_add => |air_tag| if (use_old) try cg.airMulAdd(inst) else {
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const pl_op = air_datas[@intFromEnum(inst)].pl_op;
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const bin_op = cg.air.extraData(Air.Bin, pl_op.payload).data;
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@ -94743,11 +94769,6 @@ fn airUnionInit(self: *CodeGen, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ extra.init, .none, .none });
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}
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fn airPrefetch(self: *CodeGen, inst: Air.Inst.Index) !void {
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const prefetch = self.air.instructions.items(.data)[@intFromEnum(inst)].prefetch;
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return self.finishAir(inst, .unreach, .{ prefetch.ptr, .none, .none });
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}
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fn airMulAdd(self: *CodeGen, inst: Air.Inst.Index) !void {
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const pt = self.pt;
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const zcu = pt.zcu;
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@ -78,7 +78,7 @@ pub fn findByMnemonic(
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),
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.x86_64 => false,
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},
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inline .@"invpcid 64bit", .@"rdpid 64bit" => |tag| switch (target.cpu.arch) {
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inline .@"invpcid 64bit", .@"rdpid 64bit", .@"prefetchi 64bit" => |tag| switch (target.cpu.arch) {
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else => unreachable,
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.x86 => false,
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.x86_64 => std.Target.x86.featureSetHas(
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@ -86,6 +86,7 @@ pub fn findByMnemonic(
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@field(std.Target.x86.Feature, @tagName(tag)[0 .. @tagName(tag).len - " 64bit".len]),
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),
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},
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.prefetch => std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .prfchw, .prefetchi, .prefetchwt1 }),
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inline else => |tag| has_features: {
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comptime var feature_it = std.mem.splitScalar(u8, @tagName(tag), ' ');
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comptime var features: []const std.Target.x86.Feature = &.{};
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@ -375,6 +376,7 @@ pub const Mnemonic = enum {
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orps,
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pextrw, pinsrw,
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pmaxsw, pmaxub, pminsw, pminub, pmovmskb,
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prefetchit0, prefetchit1, prefetchnta, prefetcht0, prefetcht1, prefetcht2, prefetchw, prefetchwt1,
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shufps,
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sqrtps, sqrtss,
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stmxcsr,
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@ -562,8 +564,7 @@ pub const Op = enum {
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r32_m8, r32_m16, r64_m16,
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m8, m16, m32, m64, m80, m128, m256,
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rel8, rel16, rel32,
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m,
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moffs,
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m, moffs, mrip8,
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sreg,
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st0, st, mm, mm_m64,
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xmm0, xmm, xmm_m8, xmm_m16, xmm_m32, xmm_m64, xmm_m128,
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@ -617,7 +618,7 @@ pub const Op = enum {
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.mem => |mem| switch (mem) {
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.moffs => .moffs,
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.sib, .rip => switch (mem.bitSize(target)) {
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.sib => switch (mem.bitSize(target)) {
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0 => .m,
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8 => .m8,
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16 => .m16,
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@ -628,6 +629,16 @@ pub const Op = enum {
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256 => .m256,
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else => unreachable,
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},
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.rip => switch (mem.bitSize(target)) {
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0, 8 => .mrip8,
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16 => .m16,
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32 => .m32,
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64 => .m64,
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80 => .m80,
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128 => .m128,
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256 => .m256,
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else => unreachable,
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},
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},
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.imm => |imm| switch (imm) {
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@ -680,7 +691,7 @@ pub const Op = enum {
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pub fn immBitSize(op: Op) u64 {
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return switch (op) {
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.none, .moffs, .m, .sreg => unreachable,
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.none, .m, .moffs, .mrip8, .sreg => unreachable,
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.al, .cl, .dx, .rip, .eip, .ip, .r8, .rm8, .r32_m8 => unreachable,
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.ax, .r16, .rm16 => unreachable,
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.eax, .r32, .rm32, .r32_m16 => unreachable,
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@ -700,7 +711,7 @@ pub const Op = enum {
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pub fn regBitSize(op: Op) u64 {
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return switch (op) {
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.none, .moffs, .m, .sreg => unreachable,
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.none, .m, .moffs, .mrip8, .sreg => unreachable,
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.unity, .imm8, .imm8s, .imm16, .imm16s, .imm32, .imm32s, .imm64 => unreachable,
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.rel8, .rel16, .rel32 => unreachable,
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.m8, .m16, .m32, .m64, .m80, .m128, .m256 => unreachable,
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@ -716,13 +727,13 @@ pub const Op = enum {
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pub fn memBitSize(op: Op) u64 {
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return switch (op) {
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.none, .moffs, .m, .sreg => unreachable,
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.none, .m, .moffs, .sreg => unreachable,
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.unity, .imm8, .imm8s, .imm16, .imm16s, .imm32, .imm32s, .imm64 => unreachable,
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.rel8, .rel16, .rel32 => unreachable,
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.al, .cl, .r8, .ax, .dx, .ip, .r16, .eax, .eip, .r32, .rax, .rip, .r64 => unreachable,
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.st0, .st, .mm, .xmm0, .xmm, .ymm => unreachable,
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.cr, .dr => unreachable,
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.m8, .rm8, .r32_m8, .xmm_m8 => 8,
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.mrip8, .m8, .rm8, .r32_m8, .xmm_m8 => 8,
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.m16, .rm16, .r32_m16, .r64_m16, .xmm_m16 => 16,
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.m32, .rm32, .xmm_m32 => 32,
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.m64, .rm64, .mm_m64, .xmm_m64 => 64,
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@ -783,7 +794,7 @@ pub const Op = enum {
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.rm8, .rm16, .rm32, .rm64,
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.r32_m8, .r32_m16, .r64_m16,
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.m8, .m16, .m32, .m64, .m80, .m128, .m256,
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.m,
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.m, .moffs, .mrip8,
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.mm_m64,
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.xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128,
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.ymm_m256,
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@ -821,11 +832,7 @@ pub const Op = enum {
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/// Given an operand `op` checks if `target` is a subset for the purposes of the encoding.
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pub fn isSubset(op: Op, target: Op) bool {
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switch (op) {
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.moffs, .sreg => return op == target,
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.none => switch (target) {
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.none => return true,
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else => return false,
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},
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.none, .m, .moffs, .sreg => return op == target,
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else => {
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if (op.isRegister() and target.isRegister()) {
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return switch (target.toReg()) {
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@ -836,6 +843,7 @@ pub const Op = enum {
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if (op.isMemory() and target.isMemory()) {
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switch (target) {
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.m => return true,
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.moffs, .mrip8 => return op == target,
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else => return op.memBitSize() == target.memBitSize(),
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}
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}
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@ -962,6 +970,10 @@ pub const Feature = enum {
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@"pclmul avx",
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pku,
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popcnt,
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prefetch,
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@"prefetchi 64bit",
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prefetchwt1,
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prfchw,
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rdrnd,
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rdseed,
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@"rdpid 32bit",
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@ -1002,7 +1014,7 @@ fn estimateInstructionLength(prefix: Prefix, encoding: Encoding, ops: []const Op
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}
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const mnemonic_to_encodings_map = init: {
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@setEvalBranchQuota(5_700);
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@setEvalBranchQuota(5_800);
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const mnemonic_count = @typeInfo(Mnemonic).@"enum".fields.len;
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var mnemonic_map: [mnemonic_count][]Data = @splat(&.{});
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const encodings = @import("encodings.zig");
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@ -34,8 +34,18 @@ pub const Inst = struct {
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/// ___ 4
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_4,
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/// ___ With NTA Hint
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_nta,
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/// System Call ___
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sys_,
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/// ___ With T0 Hint
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_t0,
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/// ___ With T1 Hint
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_t1,
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/// ___ With T2 Hint
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_t2,
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/// ___ With Intent to Write and T1 Hint
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_wt1,
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/// ___ crement Shadow Stack Pointer Doubleword
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_csspd,
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@ -198,6 +208,7 @@ pub const Inst = struct {
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//_b,
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/// ___ Word
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/// ___ For Writing
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/// ___ With Intent to Write
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_w,
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/// ___ Doubleword
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//_d,
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@ -975,6 +986,9 @@ pub const Inst = struct {
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/// Move unaligned packed single-precision floating-point values
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/// Move unaligned packed double-precision floating-point values
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movu,
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/// Prefetch data into caches
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/// Prefetch data into caches with intent to write
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prefetch,
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/// Packed interleave shuffle of quadruplets of single-precision floating-point values
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/// Packed interleave shuffle of pairs of double-precision floating-point values
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/// Shuffle packed doublewords
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@ -1370,6 +1370,18 @@ pub const table = [_]Entry{
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.{ .pmovmskb, .rm, &.{ .r32, .xmm }, &.{ 0x66, 0x0f, 0xd7 }, 0, .none, .sse },
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.{ .pmovmskb, .rm, &.{ .r64, .xmm }, &.{ 0x66, 0x0f, 0xd7 }, 0, .none, .sse },
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.{ .prefetchit0, .m, &.{ .mrip8 }, &.{ 0x0f, 0x18 }, 7, .none, .@"prefetchi 64bit" },
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.{ .prefetchit1, .m, &.{ .mrip8 }, &.{ 0x0f, 0x18 }, 6, .none, .@"prefetchi 64bit" },
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.{ .prefetchnta, .m, &.{ .m8 }, &.{ 0x0f, 0x18 }, 0, .none, .prefetch },
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.{ .prefetcht0, .m, &.{ .m8 }, &.{ 0x0f, 0x18 }, 1, .none, .prefetch },
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.{ .prefetcht1, .m, &.{ .m8 }, &.{ 0x0f, 0x18 }, 2, .none, .prefetch },
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.{ .prefetcht2, .m, &.{ .m8 }, &.{ 0x0f, 0x18 }, 3, .none, .prefetch },
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.{ .prefetchw, .m, &.{ .m8 }, &.{ 0x0f, 0x0d }, 1, .none, .prfchw },
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.{ .prefetchwt1, .m, &.{ .m8 }, &.{ 0x0f, 0x0d }, 2, .none, .prefetchwt1 },
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.{ .shufps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x0f, 0xc6 }, 0, .none, .sse },
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.{ .sqrtps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x51 }, 0, .none, .sse },
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