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behavior: disable tests that trigger an llvm 15 bug and assertion

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```
LLVM Emit Object... zig: llvm/include/llvm/ADT/APInt.h:840: void llvm::APInt::lshrInPlace(unsigned int): Assertion `ShiftAmt <= BitWidth && "Invalid shift amount"' failed.
Aborted
```

Tracked by #13782
This commit is contained in:
Jacob Young 2022-12-23 19:00:20 -05:00 committed by Andrew Kelley
parent c9e3524d0b
commit fc0789f8e7
2 changed files with 11 additions and 0 deletions
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5
test/behavior/bitcast.zig
View File

@ -334,6 +334,11 @@ test "comptime @bitCast packed struct to int and back" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.endian() == .Big) {
// https://github.com/ziglang/zig/issues/13782
return error.SkipZigTest;
}
const S = packed struct {
void: void = {},
uint: u8 = 13,

6
test/behavior/bugs/12169.zig
View File

@ -7,6 +7,12 @@ test {
if (builtin.zig_backend == .stage2_x86) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.endian() == .Big) {
// https://github.com/ziglang/zig/issues/13782
return error.SkipZigTest;
}
const a = @Vector(2, bool){ true, true };
const b = @Vector(1, bool){true};
try std.testing.expect(@reduce(.And, a));