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x86_64: implement float arithmetic builtins
This commit is contained in:
Jacob Young
parent
1eb023908d
commit
fbe5bf469e
@ -6570,6 +6570,34 @@ fn genBinOp(
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const lhs_ty = self.typeOf(lhs_air);
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const rhs_ty = self.typeOf(rhs_air);
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const abi_size: u32 = @intCast(lhs_ty.abiSize(mod));
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if (lhs_ty.isRuntimeFloat() and switch (lhs_ty.floatBits(self.target.*)) {
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16 => !self.hasFeature(.f16c),
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32, 64 => false,
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80, 128 => true,
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else => unreachable,
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}) {
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var callee: ["__add?f3".len]u8 = undefined;
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return self.genCall(.{ .lib = .{
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.return_type = lhs_ty.toIntern(),
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.param_types = &.{ lhs_ty.toIntern(), rhs_ty.toIntern() },
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.callee = switch (air_tag) {
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.add, .sub, .mul, .div_float => std.fmt.bufPrint(&callee, "__{s}{c}f3", .{
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@tagName(air_tag)[0..3],
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floatCompilerRtAbiName(lhs_ty.floatBits(self.target.*)),
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}),
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.min, .max => std.fmt.bufPrint(&callee, "{s}f{s}{s}", .{
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floatLibcAbiPrefix(lhs_ty),
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@tagName(air_tag),
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floatLibcAbiSuffix(lhs_ty),
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}),
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else => return self.fail("TODO implement genBinOp for {s} {}", .{
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@tagName(air_tag), lhs_ty.fmt(self.bin_file.options.module.?),
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}),
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} catch unreachable,
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} }, &.{ lhs_ty, rhs_ty }, &.{ .{ .air_ref = lhs_air }, .{ .air_ref = rhs_air } });
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}
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if ((lhs_ty.scalarType(mod).isRuntimeFloat() and
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lhs_ty.scalarType(mod).floatBits(self.target.*) == 80) or
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lhs_ty.abiSize(mod) > @as(u6, if (self.hasFeature(.avx)) 32 else 16))
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@ -6830,7 +6858,8 @@ fn genBinOp(
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const mir_tag = @as(?Mir.Inst.FixedTag, switch (lhs_ty.zigTypeTag(mod)) {
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else => unreachable,
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.Float => switch (lhs_ty.floatBits(self.target.*)) {
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16 => if (self.hasFeature(.f16c)) {
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16 => {
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assert(self.hasFeature(.f16c));
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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@ -6873,7 +6902,7 @@ fn genBinOp(
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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} else null,
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},
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32 => switch (air_tag) {
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.add => if (self.hasFeature(.avx)) .{ .v_ss, .add } else .{ ._ss, .add },
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.sub => if (self.hasFeature(.avx)) .{ .v_ss, .sub } else .{ ._ss, .sub },
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@ -7134,181 +7163,184 @@ fn genBinOp(
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else => null,
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},
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.Float => switch (lhs_ty.childType(mod).floatBits(self.target.*)) {
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16 => if (self.hasFeature(.f16c)) switch (lhs_ty.vectorLen(mod)) {
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1 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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16 => tag: {
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assert(self.hasFeature(.f16c));
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switch (lhs_ty.vectorLen(mod)) {
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1 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
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.{ .vp_w, .insr },
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dst_reg,
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dst_reg,
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src_mcv.mem(.word),
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Immediate.u(1),
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) else try self.asmRegisterRegisterRegister(
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.{ .vp_, .unpcklwd },
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dst_reg,
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dst_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
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try self.asmRegisterRegister(.{ .v_, .movshdup }, tmp_reg, dst_reg);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ss, .add },
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.sub => .{ .v_ss, .sub },
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.mul => .{ .v_ss, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ss, .div },
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.max => .{ .v_ss, .max },
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.min => .{ .v_ss, .max },
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else => unreachable,
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},
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dst_reg,
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dst_reg,
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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2 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
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.{ .vp_w, .insr },
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dst_reg,
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dst_reg,
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src_mcv.mem(.word),
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Immediate.u(1),
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) else try self.asmRegisterRegisterRegister(
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.{ .vp_, .unpcklwd },
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dst_reg,
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dst_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
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try self.asmRegisterRegister(.{ .v_, .movshdup }, tmp_reg, dst_reg);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ss, .add },
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.sub => .{ .v_ss, .sub },
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.mul => .{ .v_ss, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ss, .div },
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.max => .{ .v_ss, .max },
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.min => .{ .v_ss, .max },
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else => unreachable,
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},
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dst_reg,
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dst_reg,
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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2 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate(
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.{ .vp_d, .insr },
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dst_reg,
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src_mcv.mem(.dword),
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Immediate.u(1),
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) else try self.asmRegisterRegisterRegister(
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.{ .v_ps, .unpckl },
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dst_reg,
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dst_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
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try self.asmRegisterRegisterRegister(
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.{ .v_ps, .movhl },
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tmp_reg,
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dst_reg,
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dst_reg,
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);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ps, .add },
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.sub => .{ .v_ps, .sub },
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.mul => .{ .v_ps, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
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.max => .{ .v_ps, .max },
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.min => .{ .v_ps, .max },
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else => unreachable,
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},
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dst_reg,
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dst_reg,
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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3...4 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate(
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.{ .vp_d, .insr },
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dst_reg,
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src_mcv.mem(.dword),
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Immediate.u(1),
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) else try self.asmRegisterRegisterRegister(
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.{ .v_ps, .unpckl },
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dst_reg,
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dst_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
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try self.asmRegisterRegisterRegister(
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.{ .v_ps, .movhl },
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tmp_reg,
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dst_reg,
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dst_reg,
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);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ps, .add },
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.sub => .{ .v_ps, .sub },
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.mul => .{ .v_ps, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
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.max => .{ .v_ps, .max },
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.min => .{ .v_ps, .max },
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else => unreachable,
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},
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dst_reg,
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dst_reg,
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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3...4 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to128();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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src_mcv.mem(.qword),
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) else try self.asmRegisterRegister(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ps, .add },
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.sub => .{ .v_ps, .sub },
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.mul => .{ .v_ps, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
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.max => .{ .v_ps, .max },
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.min => .{ .v_ps, .max },
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else => unreachable,
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},
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dst_reg,
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dst_reg,
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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5...8 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to256();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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src_mcv.mem(.qword),
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) else try self.asmRegisterRegister(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ps, .add },
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.sub => .{ .v_ps, .sub },
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.mul => .{ .v_ps, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
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.max => .{ .v_ps, .max },
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.min => .{ .v_ps, .max },
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else => unreachable,
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},
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dst_reg,
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dst_reg,
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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5...8 => {
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const tmp_reg = (try self.register_manager.allocReg(null, sse)).to256();
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg.to256(), dst_reg);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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src_mcv.mem(.xword),
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) else try self.asmRegisterRegister(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ps, .add },
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.sub => .{ .v_ps, .sub },
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.mul => .{ .v_ps, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
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.max => .{ .v_ps, .max },
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.min => .{ .v_ps, .max },
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else => unreachable,
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},
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dst_reg.to256(),
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dst_reg.to256(),
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg.to256(),
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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else => null,
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} else null,
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try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg.to256(), dst_reg);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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src_mcv.mem(.xword),
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) else try self.asmRegisterRegister(
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.{ .v_ps, .cvtph2 },
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tmp_reg,
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
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);
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try self.asmRegisterRegisterRegister(
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switch (air_tag) {
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.add => .{ .v_ps, .add },
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.sub => .{ .v_ps, .sub },
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.mul => .{ .v_ps, .mul },
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.div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
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.max => .{ .v_ps, .max },
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.min => .{ .v_ps, .max },
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else => unreachable,
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},
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dst_reg.to256(),
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dst_reg.to256(),
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tmp_reg,
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);
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try self.asmRegisterRegisterImmediate(
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.{ .v_, .cvtps2ph },
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dst_reg,
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dst_reg.to256(),
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Immediate.u(0b1_00),
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);
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return dst_mcv;
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},
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else => break :tag null,
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}
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},
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32 => switch (lhs_ty.vectorLen(mod)) {
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1 => switch (air_tag) {
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.add => if (self.hasFeature(.avx)) .{ .v_ss, .add } else .{ ._ss, .add },
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@ -19,6 +19,99 @@ fn epsForType(comptime T: type) T {
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};
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}
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test "add f16" {
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
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try testAdd(f16);
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try comptime testAdd(f16);
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}
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test "add f32/f64" {
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try testAdd(f32);
|
||||
try comptime testAdd(f32);
|
||||
try testAdd(f64);
|
||||
try comptime testAdd(f64);
|
||||
}
|
||||
|
||||
test "add f80/f128/c_longdouble" {
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
|
||||
try testAdd(f80);
|
||||
try comptime testAdd(f80);
|
||||
try testAdd(f128);
|
||||
try comptime testAdd(f128);
|
||||
try testAdd(c_longdouble);
|
||||
try comptime testAdd(c_longdouble);
|
||||
}
|
||||
|
||||
fn testAdd(comptime T: type) !void {
|
||||
var one_point_two_five: T = 1.25;
|
||||
var two_point_seven_five: T = 2.75;
|
||||
try expect(one_point_two_five + two_point_seven_five == 4);
|
||||
}
|
||||
|
||||
test "sub f16" {
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
|
||||
try testSub(f16);
|
||||
try comptime testSub(f16);
|
||||
}
|
||||
|
||||
test "sub f32/f64" {
|
||||
try testSub(f32);
|
||||
try comptime testSub(f32);
|
||||
try testSub(f64);
|
||||
try comptime testSub(f64);
|
||||
}
|
||||
|
||||
test "sub f80/f128/c_longdouble" {
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
|
||||
try testSub(f80);
|
||||
try comptime testSub(f80);
|
||||
try testSub(f128);
|
||||
try comptime testSub(f128);
|
||||
try testSub(c_longdouble);
|
||||
try comptime testSub(c_longdouble);
|
||||
}
|
||||
|
||||
fn testSub(comptime T: type) !void {
|
||||
var one_point_two_five: T = 1.25;
|
||||
var two_point_seven_five: T = 2.75;
|
||||
try expect(one_point_two_five - two_point_seven_five == -1.5);
|
||||
}
|
||||
|
||||
test "mul f16" {
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
|
||||
try testMul(f16);
|
||||
try comptime testMul(f16);
|
||||
}
|
||||
|
||||
test "mul f32/f64" {
|
||||
try testMul(f32);
|
||||
try comptime testMul(f32);
|
||||
try testMul(f64);
|
||||
try comptime testMul(f64);
|
||||
}
|
||||
|
||||
test "mul f80/f128/c_longdouble" {
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
|
||||
try testMul(f80);
|
||||
try comptime testMul(f80);
|
||||
try testMul(f128);
|
||||
try comptime testMul(f128);
|
||||
try testMul(c_longdouble);
|
||||
try comptime testMul(c_longdouble);
|
||||
}
|
||||
|
||||
fn testMul(comptime T: type) !void {
|
||||
var one_point_two_five: T = 1.25;
|
||||
var two_point_seven_five: T = 2.75;
|
||||
try expect(one_point_two_five * two_point_seven_five == 3.4375);
|
||||
}
|
||||
|
||||
test "cmp f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
@ -216,7 +309,7 @@ test "more @sqrt f16 tests" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
|
||||
// TODO these are not all passing at comptime
|
||||
try expect(@sqrt(@as(f16, 0.0)) == 0.0);
|
||||
@ -269,7 +362,6 @@ test "@sin f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testSin(f16);
|
||||
try comptime testSin(f16);
|
||||
@ -339,7 +431,6 @@ test "@cos f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testCos(f16);
|
||||
try comptime testCos(f16);
|
||||
@ -409,7 +500,6 @@ test "@tan f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testTan(f16);
|
||||
try comptime testTan(f16);
|
||||
@ -479,7 +569,6 @@ test "@exp f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testExp(f16);
|
||||
try comptime testExp(f16);
|
||||
@ -549,7 +638,6 @@ test "@exp2 f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testExp2(f16);
|
||||
try comptime testExp2(f16);
|
||||
@ -619,7 +707,6 @@ test "@log f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testLog(f16);
|
||||
try comptime testLog(f16);
|
||||
@ -687,7 +774,6 @@ test "@log2 f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testLog2(f16);
|
||||
try comptime testLog2(f16);
|
||||
@ -761,7 +847,6 @@ test "@log10 f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
|
||||
try testLog10(f16);
|
||||
try comptime testLog10(f16);
|
||||
@ -829,7 +914,7 @@ test "@abs f16" {
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
|
||||
try testFabs(f16);
|
||||
try comptime testFabs(f16);
|
||||
@ -1186,7 +1271,7 @@ test "neg f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
|
||||
if (builtin.os.tag == .freebsd) {
|
||||
// TODO file issue to track this failure
|
||||
|
||||
@ -7,8 +7,6 @@ const maxInt = std.math.maxInt;
|
||||
const minInt = std.math.minInt;
|
||||
const mem = std.mem;
|
||||
const math = std.math;
|
||||
const no_x86_64_hardware_f16_support = builtin.zig_backend == .stage2_x86_64 and
|
||||
!std.Target.x86.featureSetHas(builtin.cpu.features, .f16c);
|
||||
|
||||
test "assignment operators" {
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -1444,7 +1442,6 @@ test "@round f16" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
|
||||
if (no_x86_64_hardware_f16_support) return error.SkipZigTest; // TODO
|
||||
|
||||
try testRound(f16, 12.0);
|
||||
try comptime testRound(f16, 12.0);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user