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stage2 sparcv9: Add Format 2 encoder
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048035ea55
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@ -460,4 +460,72 @@ pub const Instruction = union(enum) {
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.disp30 = udisp,
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} };
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}
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fn format2a(rd: Register, op2: u3, imm: i22) Instruction {
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const umm = @bitCast(u22, imm);
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return Instruction{
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.format_2a = .{
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.rd = rd.enc(),
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.op2 = op2,
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.imm22 = umm,
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},
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};
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}
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fn format2b(a: u1, cond: u4, op2: u3, disp: i24) Instruction {
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// In SPARC, branch target needs to be aligned to 4 bytes.
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assert(disp % 4 == 0);
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// Discard the last two bits since those are implicitly zero.
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const udisp = @truncate(u22, @bitCast(u24, disp) >> 2);
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return Instruction{
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.format_2b = .{
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.a = a,
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.cond = cond,
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.op2 = op2,
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.disp22 = udisp,
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},
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};
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}
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fn format2c(a: u1, cond: u4, op2: u3, cc1: u1, cc0: u1, p: u1, disp: i21) Instruction {
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// In SPARC, branch target needs to be aligned to 4 bytes.
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assert(disp % 4 == 0);
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// Discard the last two bits since those are implicitly zero.
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const udisp = @truncate(u19, @bitCast(u21, disp) >> 2);
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return Instruction{
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.format_2c = .{
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.a = a,
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.cond = cond,
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.op2 = op2,
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.cc1 = cc1,
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.cc0 = cc0,
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.p = p,
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.disp19 = udisp,
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},
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};
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}
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fn format2d(a: u1, rcond: u3, op2: u3, p: u1, rs1: Register, disp: i18) Instruction {
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// In SPARC, branch target needs to be aligned to 4 bytes.
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assert(disp % 4 == 0);
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// Discard the last two bits since those are implicitly zero,
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// and split it into low and high parts.
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const udisp = @truncate(u16, @bitCast(u18, disp) >> 2);
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const udisp_hi = @truncate(u2, (udisp & 0b1100_0000_0000_0000) >> 14);
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const udisp_lo = @truncate(u14, udisp & 0b0011_1111_1111_1111);
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return Instruction{
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.format_2a = .{
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.a = a,
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.rcond = rcond,
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.op2 = op2,
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.p = p,
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.rs1 = rs1.enc(),
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.d16hi = udisp_hi,
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.d16lo = udisp_lo,
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},
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};
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}
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};
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