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https://github.com/ziglang/zig.git
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x86_64: simplify immediate handling at MIR level
This commit is contained in:
Jakub Konka
parent
0a8b5c20aa
commit
fb38e3d6b2
@ -460,15 +460,13 @@ fn asmRegister(self: *Self, tag: Mir.Inst.Tag, reg: Register) !void {
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fn asmImmediate(self: *Self, tag: Mir.Inst.Tag, imm: Immediate) !void {
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const ops: Mir.Inst.Ops = if (imm == .signed) .imm_s else .imm_u;
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const data: Mir.Inst.Data = switch (ops) {
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.imm_s => .{ .imm_s = imm.signed },
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.imm_u => .{ .imm_u = @intCast(u32, imm.unsigned) },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = ops,
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.data = data,
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.data = .{ .imm = switch (imm) {
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.signed => |x| @bitCast(u32, x),
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.unsigned => |x| @intCast(u32, x),
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} },
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});
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}
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@ -489,11 +487,11 @@ fn asmRegisterImmediate(self: *Self, tag: Mir.Inst.Tag, reg: Register, imm: Imme
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.unsigned => |x| if (x <= math.maxInt(u32)) .ri_u else .ri64,
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};
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const data: Mir.Inst.Data = switch (ops) {
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.ri_s => .{ .ri_s = .{
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.ri_s => .{ .ri = .{
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.r1 = reg,
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.imm = imm.signed,
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.imm = @bitCast(u32, imm.signed),
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} },
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.ri_u => .{ .ri_u = .{
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.ri_u => .{ .ri = .{
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.r1 = reg,
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.imm = @intCast(u32, imm.unsigned),
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} },
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@ -522,12 +520,12 @@ fn asmRegisterRegisterImmediate(
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.unsigned => .rri_u,
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};
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const data: Mir.Inst.Data = switch (ops) {
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.rri_s => .{ .rri_s = .{
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.rri_s => .{ .rri = .{
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.r1 = reg1,
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.r2 = reg2,
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.imm = imm.signed,
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.imm = @bitCast(u32, imm.signed),
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} },
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.rri_u => .{ .rri_u = .{
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.rri_u => .{ .rri = .{
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.r1 = reg1,
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.r2 = reg2,
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.imm = @intCast(u32, imm.unsigned),
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@ -547,11 +545,11 @@ fn asmMemory(self: *Self, tag: Mir.Inst.Tag, m: Memory) !void {
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.rip => .m_rip,
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else => unreachable,
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};
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const data: Mir.Inst.Data = switch (ops) {
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.m_sib => .{ .payload = try self.addExtra(Mir.MemorySib.encode(m)) },
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.m_rip => .{ .payload = try self.addExtra(Mir.MemoryRip.encode(m)) },
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const data: Mir.Inst.Data = .{ .payload = switch (ops) {
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.m_sib => try self.addExtra(Mir.MemorySib.encode(m)),
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.m_rip => try self.addExtra(Mir.MemoryRip.encode(m)),
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else => unreachable,
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};
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} };
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_ = try self.addInst(.{
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.tag = tag,
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.ops = ops,
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@ -570,10 +568,11 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.Tag, m: Memory, imm: Immediate)
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.mi_s_rip, .mi_u_rip => try self.addExtra(Mir.MemoryRip.encode(m)),
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else => unreachable,
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};
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const data: Mir.Inst.Data = switch (ops) {
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.mi_s_sib, .mi_s_rip => .{ .xi_s = .{ .imm = imm.signed, .payload = payload } },
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.mi_u_sib, .mi_u_rip => .{ .xi_u = .{ .imm = @intCast(u32, imm.unsigned), .payload = payload } },
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else => unreachable,
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const data: Mir.Inst.Data = .{
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.xi = .{ .payload = payload, .imm = switch (imm) {
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.signed => |x| @bitCast(u32, x),
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.unsigned => |x| @intCast(u32, x),
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} },
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};
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_ = try self.addInst(.{
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.tag = tag,
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@ -588,16 +587,12 @@ fn asmRegisterMemory(self: *Self, tag: Mir.Inst.Tag, reg: Register, m: Memory) !
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.rip => .rm_rip,
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else => unreachable,
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};
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const data: Mir.Inst.Data = switch (ops) {
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.rm_sib => .{ .rx = .{
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.r1 = reg,
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.payload = try self.addExtra(Mir.MemorySib.encode(m)),
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const data: Mir.Inst.Data = .{
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.rx = .{ .r1 = reg, .payload = switch (ops) {
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.rm_sib => try self.addExtra(Mir.MemorySib.encode(m)),
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.rm_rip => try self.addExtra(Mir.MemoryRip.encode(m)),
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else => unreachable,
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} },
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.rm_rip => .{ .rx = .{
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.r1 = reg,
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.payload = try self.addExtra(Mir.MemoryRip.encode(m)),
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = tag,
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@ -612,16 +607,12 @@ fn asmMemoryRegister(self: *Self, tag: Mir.Inst.Tag, m: Memory, reg: Register) !
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.rip => .mr_rip,
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else => unreachable,
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};
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const data: Mir.Inst.Data = switch (ops) {
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.mr_sib => .{ .rx = .{
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.r1 = reg,
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.payload = try self.addExtra(Mir.MemorySib.encode(m)),
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const data: Mir.Inst.Data = .{
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.rx = .{ .r1 = reg, .payload = switch (ops) {
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.mr_sib => try self.addExtra(Mir.MemorySib.encode(m)),
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.mr_rip => try self.addExtra(Mir.MemoryRip.encode(m)),
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else => unreachable,
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} },
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.mr_rip => .{ .rx = .{
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.r1 = reg,
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.payload = try self.addExtra(Mir.MemoryRip.encode(m)),
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = tag,
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@ -733,7 +724,7 @@ fn gen(self: *Self) InnerError!void {
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self.mir_instructions.set(backpatch_stack_sub, .{
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.tag = .sub,
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.ops = .ri_u,
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.data = .{ .ri_u = .{
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.data = .{ .ri = .{
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.r1 = .rsp,
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.imm = aligned_stack_end,
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} },
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@ -741,7 +732,7 @@ fn gen(self: *Self) InnerError!void {
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self.mir_instructions.set(backpatch_stack_add, .{
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.tag = .add,
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.ops = .ri_u,
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.data = .{ .ri_u = .{
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.data = .{ .ri = .{
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.r1 = .rsp,
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.imm = aligned_stack_end,
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} },
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@ -5602,7 +5593,7 @@ fn genInlineMemcpy(
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const loop_start = try self.addInst(.{
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.tag = .cmp,
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.ops = .ri_u,
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.data = .{ .ri_u = .{
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.data = .{ .ri = .{
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.r1 = count_reg,
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.imm = 0,
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} },
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@ -5681,9 +5672,9 @@ fn genInlineMemset(
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const loop_start = try self.addInst(.{
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.tag = .cmp,
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.ops = .ri_s,
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.data = .{ .ri_s = .{
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.data = .{ .ri = .{
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.r1 = index_reg,
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.imm = -1,
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.imm = @bitCast(u32, @as(i32, -1)),
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} },
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});
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const loop_reloc = try self.asmJccReloc(undefined, .e);
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@ -194,105 +194,115 @@ fn mirEncodeGeneric(emit: *Emit, tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerE
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const ops = emit.mir.instructions.items(.ops)[inst];
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const data = emit.mir.instructions.items(.data)[inst];
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var operands = [4]Instruction.Operand{ .none, .none, .none, .none };
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var op1: Instruction.Operand = .none;
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var op2: Instruction.Operand = .none;
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var op3: Instruction.Operand = .none;
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var op4: Instruction.Operand = .none;
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switch (ops) {
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.none => {},
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.imm_s => operands[0] = .{ .imm = Immediate.s(data.imm_s) },
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.imm_u => operands[0] = .{ .imm = Immediate.u(data.imm_u) },
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.r => operands[0] = .{ .reg = data.r },
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.rr => operands[0..2].* = .{
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.{ .reg = data.rr.r1 },
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.{ .reg = data.rr.r2 },
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.imm_s => op1 = .{ .imm = Immediate.s(@bitCast(i32, data.imm)) },
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.imm_u => op1 = .{ .imm = Immediate.u(data.imm) },
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.r => op1 = .{ .reg = data.r },
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.rr => {
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op1 = .{ .reg = data.rr.r1 };
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op2 = .{ .reg = data.rr.r2 };
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},
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.ri_s => operands[0..2].* = .{
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.{ .reg = data.ri_s.r1 },
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.{ .imm = Immediate.s(data.ri_s.imm) },
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},
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.ri_u => operands[0..2].* = .{
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.{ .reg = data.ri_u.r1 },
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.{ .imm = Immediate.u(data.ri_u.imm) },
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.ri_s, .ri_u => {
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const imm = switch (ops) {
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.ri_s => Immediate.s(@bitCast(i32, data.ri.imm)),
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.ri_u => Immediate.u(data.ri.imm),
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else => unreachable,
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};
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op1 = .{ .reg = data.ri.r1 };
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op2 = .{ .imm = imm };
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},
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.ri64 => {
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const imm64 = emit.mir.extraData(Mir.Imm64, data.rx.payload).data;
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operands[0..2].* = .{
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.{ .reg = data.rx.r1 },
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.{ .imm = Immediate.u(Mir.Imm64.decode(imm64)) },
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op1 = .{ .reg = data.rx.r1 };
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op2 = .{ .imm = Immediate.u(Mir.Imm64.decode(imm64)) };
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},
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.rri_s, .rri_u => {
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const imm = switch (ops) {
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.rri_s => Immediate.s(@bitCast(i32, data.rri.imm)),
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.rri_u => Immediate.u(data.rri.imm),
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else => unreachable,
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};
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},
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.rri_s => operands[0..3].* = .{
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.{ .reg = data.rri_s.r1 },
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.{ .reg = data.rri_s.r2 },
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.{ .imm = Immediate.s(data.rri_s.imm) },
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},
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.rri_u => operands[0..3].* = .{
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.{ .reg = data.rri_u.r1 },
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.{ .reg = data.rri_u.r2 },
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.{ .imm = Immediate.u(data.rri_u.imm) },
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op1 = .{ .reg = data.rri.r1 };
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op2 = .{ .reg = data.rri.r2 };
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op3 = .{ .imm = imm };
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},
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.m_sib => {
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const msib = emit.mir.extraData(Mir.MemorySib, data.payload).data;
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operands[0] = .{ .mem = Mir.MemorySib.decode(msib) };
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op1 = .{ .mem = Mir.MemorySib.decode(msib) };
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},
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.m_rip => {
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const mrip = emit.mir.extraData(Mir.MemoryRip, data.payload).data;
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operands[0] = .{ .mem = Mir.MemoryRip.decode(mrip) };
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op1 = .{ .mem = Mir.MemoryRip.decode(mrip) };
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},
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.mi_u_sib => {
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const msib = emit.mir.extraData(Mir.MemorySib, data.xi_u.payload).data;
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operands[0..2].* = .{
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.{ .mem = Mir.MemorySib.decode(msib) },
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.{ .imm = Immediate.u(data.xi_u.imm) },
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.mi_s_sib, .mi_u_sib => {
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const msib = emit.mir.extraData(Mir.MemorySib, data.xi.payload).data;
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const imm = switch (ops) {
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.mi_s_sib => Immediate.s(@bitCast(i32, data.xi.imm)),
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.mi_u_sib => Immediate.u(data.xi.imm),
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else => unreachable,
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};
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op1 = .{ .mem = Mir.MemorySib.decode(msib) };
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op2 = .{ .imm = imm };
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},
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.mi_s_sib => {
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const msib = emit.mir.extraData(Mir.MemorySib, data.xi_s.payload).data;
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operands[0..2].* = .{
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.{ .mem = Mir.MemorySib.decode(msib) },
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.{ .imm = Immediate.s(data.xi_s.imm) },
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};
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},
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.mi_u_rip => {
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const mrip = emit.mir.extraData(Mir.MemoryRip, data.xi_u.payload).data;
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operands[0..2].* = .{
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.{ .mem = Mir.MemoryRip.decode(mrip) },
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.{ .imm = Immediate.u(data.xi_u.imm) },
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};
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},
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.mi_s_rip => {
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const mrip = emit.mir.extraData(Mir.MemoryRip, data.xi_s.payload).data;
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operands[0..2].* = .{
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.{ .mem = Mir.MemoryRip.decode(mrip) },
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.{ .imm = Immediate.s(data.xi_s.imm) },
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.mi_u_rip, .mi_s_rip => {
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const mrip = emit.mir.extraData(Mir.MemoryRip, data.xi.payload).data;
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const imm = switch (ops) {
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.mi_s_rip => Immediate.s(@bitCast(i32, data.xi.imm)),
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.mi_u_rip => Immediate.u(data.xi.imm),
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else => unreachable,
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};
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op1 = .{ .mem = Mir.MemoryRip.decode(mrip) };
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op2 = .{ .imm = imm };
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},
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.rm_sib, .mr_sib => {
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const msib = emit.mir.extraData(Mir.MemorySib, data.rx.payload).data;
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const op1 = .{ .reg = data.rx.r1 };
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const op2 = .{ .mem = Mir.MemorySib.decode(msib) };
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const op_r = .{ .reg = data.rx.r1 };
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const op_m = .{ .mem = Mir.MemorySib.decode(msib) };
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switch (ops) {
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.rm_sib => operands[0..2].* = .{ op1, op2 },
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.mr_sib => operands[0..2].* = .{ op2, op1 },
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.rm_sib => {
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op1 = op_r;
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op2 = op_m;
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},
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.mr_sib => {
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op1 = op_m;
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op2 = op_r;
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},
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else => unreachable,
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}
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},
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.rm_rip, .mr_rip => {
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const mrip = emit.mir.extraData(Mir.MemoryRip, data.rx.payload).data;
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const op1 = .{ .reg = data.rx.r1 };
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const op2 = .{ .mem = Mir.MemoryRip.decode(mrip) };
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const op_r = .{ .reg = data.rx.r1 };
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const op_m = .{ .mem = Mir.MemoryRip.decode(mrip) };
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switch (ops) {
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.rm_rip => operands[0..2].* = .{ op1, op2 },
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.mr_rip => operands[0..2].* = .{ op2, op1 },
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.rm_sib => {
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op1 = op_r;
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op2 = op_m;
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},
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.mr_sib => {
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op1 = op_m;
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op2 = op_r;
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},
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else => unreachable,
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}
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},
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else => unreachable, // TODO
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else => return emit.fail("TODO handle generic encoding: {s}, {s}", .{
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@tagName(mnemonic),
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@tagName(ops),
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}),
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}
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return emit.encode(mnemonic, .{
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.op1 = operands[0],
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.op2 = operands[1],
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.op3 = operands[2],
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.op4 = operands[3],
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.op1 = op1,
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.op2 = op2,
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.op3 = op3,
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.op4 = op4,
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});
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}
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@ -182,10 +182,10 @@ pub const Inst = struct {
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/// Uses `rrr` payload.
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rrr,
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/// Register, register, immediate (sign-extended) operands.
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/// Uses `rri_s` payload.
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/// Uses `rri` payload.
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rri_s,
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/// Register, register, immediate (unsigned) operands.
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/// Uses `rri_u` payload.
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/// Uses `rri` payload.
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rri_u,
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/// Register with condition code (CC).
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/// Uses `r_c` payload.
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@ -194,22 +194,22 @@ pub const Inst = struct {
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/// Uses `rr_c` payload.
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rr_c,
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/// Register, immediate (sign-extended) operands.
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/// Uses `ri_s` payload.
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/// Uses `ri` payload.
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ri_s,
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/// Register, immediate (unsigned) operands.
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/// Uses `ri_u` payload.
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/// Uses `ri` payload.
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ri_u,
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/// Register, 64-bit unsigned immediate operands.
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/// Uses `rx` payload with payload type `Imm64`.
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ri64,
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/// Immediate (sign-extended) operand.
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/// Uses `imm_s` payload.
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/// Uses `imm` payload.
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imm_s,
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/// Immediate (unsigned) operand.
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/// Uses `imm_u` payload.
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/// Uses `imm` payload.
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imm_u,
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/// Relative displacement operand.
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/// Uses `rel` payload.
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/// Uses `imm` payload.
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rel,
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/// Register, memory (SIB) operands.
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/// Uses `rx` payload.
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@ -224,16 +224,16 @@ pub const Inst = struct {
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/// Uses `payload` with extra data of type `MemoryRip`.
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m_rip,
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/// Memory (SIB), immediate (unsigned) operands.
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||||
/// Uses `xi_u` payload with extra data of type `MemorySib`.
|
||||
/// Uses `xi` payload with extra data of type `MemorySib`.
|
||||
mi_u_sib,
|
||||
/// Memory (RIP), immediate (unsigned) operands.
|
||||
/// Uses `xi_u` payload with extra data of type `MemoryRip`.
|
||||
/// Uses `xi` payload with extra data of type `MemoryRip`.
|
||||
mi_u_rip,
|
||||
/// Memory (SIB), immediate (sign-extend) operands.
|
||||
/// Uses `xi_s` payload with extra data of type `MemorySib`.
|
||||
/// Uses `xi` payload with extra data of type `MemorySib`.
|
||||
mi_s_sib,
|
||||
/// Memory (RIP), immediate (sign-extend) operands.
|
||||
/// Uses `xi_s` payload with extra data of type `MemoryRip`.
|
||||
/// Uses `xi` payload with extra data of type `MemoryRip`.
|
||||
mi_s_rip,
|
||||
/// Memory (SIB), register operands.
|
||||
/// Uses `rx` payload with extra data of type `MemorySib`.
|
||||
@ -281,12 +281,8 @@ pub const Inst = struct {
|
||||
/// A condition code for use with EFLAGS register.
|
||||
cc: bits.Condition,
|
||||
},
|
||||
/// A 32-bit signed immediate value.
|
||||
imm_s: i32,
|
||||
/// A 32-bit unsigned immediate value.
|
||||
imm_u: u32,
|
||||
/// A 32-bit signed relative offset value.
|
||||
rel: i32,
|
||||
/// A 32-bit immediate value.
|
||||
imm: u32,
|
||||
r: Register,
|
||||
rr: struct {
|
||||
r1: Register,
|
||||
@ -297,12 +293,7 @@ pub const Inst = struct {
|
||||
r2: Register,
|
||||
r3: Register,
|
||||
},
|
||||
rri_s: struct {
|
||||
r1: Register,
|
||||
r2: Register,
|
||||
imm: i32,
|
||||
},
|
||||
rri_u: struct {
|
||||
rri: struct {
|
||||
r1: Register,
|
||||
r2: Register,
|
||||
imm: u32,
|
||||
@ -318,13 +309,8 @@ pub const Inst = struct {
|
||||
r2: Register,
|
||||
cc: bits.Condition,
|
||||
},
|
||||
/// Register, signed immediate.
|
||||
ri_s: struct {
|
||||
r1: Register,
|
||||
imm: i32,
|
||||
},
|
||||
/// Register, unsigned immediate.
|
||||
ri_u: struct {
|
||||
/// Register, immediate.
|
||||
ri: struct {
|
||||
r1: Register,
|
||||
imm: u32,
|
||||
},
|
||||
@ -333,16 +319,11 @@ pub const Inst = struct {
|
||||
r1: Register,
|
||||
payload: u32,
|
||||
},
|
||||
/// Custom payload followed by an unsigned immediate.
|
||||
xi_u: struct {
|
||||
/// Custom payload followed by an immediate.
|
||||
xi: struct {
|
||||
payload: u32,
|
||||
imm: u32,
|
||||
},
|
||||
/// Custom payload followed by a signed immediate.
|
||||
xi_s: struct {
|
||||
payload: u32,
|
||||
imm: i32,
|
||||
},
|
||||
/// Relocation for the linker where:
|
||||
/// * `atom_index` is the index of the source
|
||||
/// * `sym_index` is the index of the target
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user