mirror of
https://github.com/ziglang/zig.git
synced 2026-02-13 12:59:04 +00:00
Cleaned up RISC-V instruction creation, added 32-bit immediates (#6077)
* Implemented all R-type arithmetic/logical instructions * Implemented all I-type arithmetic/logical instructions * Implemented all load and store instructions * Implemented all of RV64I except FENCE
This commit is contained in:
Eleanor Bartle
GitHub
parent
3cc1f8b624
commit
fa8935426b
@ -1113,11 +1113,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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try self.code.append(0xcc); // int3
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},
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.riscv64 => {
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const full = @bitCast(u32, instructions.CallBreak{
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.mode = @enumToInt(instructions.CallBreak.Mode.ebreak),
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});
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), full);
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ebreak.toU32());
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},
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else => return self.fail(src, "TODO implement @breakpoint() for {}", .{self.target.cpu.arch}),
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}
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@ -1193,12 +1189,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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const got_addr = @intCast(u32, got.p_vaddr + func.owner_decl.link.elf.offset_table_index * ptr_bytes);
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try self.genSetReg(inst.base.src, .ra, .{ .memory = got_addr });
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const jalr = instructions.Jalr{
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.rd = Register.ra.id(),
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.rs1 = Register.ra.id(),
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.offset = 0,
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};
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), @bitCast(u32, jalr));
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.ra, 0, .ra).toU32());
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} else {
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return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{});
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}
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@ -1255,12 +1246,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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try self.exitlude_jump_relocs.append(self.gpa, self.code.items.len - 4);
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},
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.riscv64 => {
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const jalr = instructions.Jalr{
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.rd = Register.zero.id(),
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.rs1 = Register.ra.id(),
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.offset = 0,
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};
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), @bitCast(u32, jalr));
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.zero, 0, .ra).toU32());
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},
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else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}),
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}
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@ -1512,11 +1498,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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}
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if (mem.eql(u8, inst.asm_source, "ecall")) {
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const full = @bitCast(u32, instructions.CallBreak{
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.mode = @enumToInt(instructions.CallBreak.Mode.ecall),
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});
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), full);
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ecall.toU32());
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} else {
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return self.fail(inst.base.src, "TODO implement support for more riscv64 assembly instructions", .{});
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}
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@ -1723,36 +1705,17 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.immediate => |unsigned_x| {
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const x = @bitCast(i64, unsigned_x);
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if (math.minInt(i12) <= x and x <= math.maxInt(i12)) {
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const instruction = @bitCast(u32, instructions.Addi{
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.mode = @enumToInt(instructions.Addi.Mode.addi),
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.imm = @truncate(i12, x),
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.rs1 = Register.zero.id(),
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.rd = reg.id(),
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});
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), instruction);
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.addi(reg, .zero, @truncate(i12, x)).toU32());
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return;
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}
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if (math.minInt(i32) <= x and x <= math.maxInt(i32)) {
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const split = @bitCast(packed struct {
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low12: i12,
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up20: i20,
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}, @truncate(i32, x));
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if (split.low12 < 0) return self.fail(src, "TODO support riscv64 genSetReg i32 immediates with 12th bit set to 1", .{});
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const lo12 = @truncate(i12, x);
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const carry: i32 = if (lo12 < 0) 1 else 0;
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const hi20 = @truncate(i20, (x >> 12) +% carry);
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const lui = @bitCast(u32, instructions.Lui{
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.imm = split.up20,
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.rd = reg.id(),
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});
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), lui);
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const addi = @bitCast(u32, instructions.Addi{
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.mode = @enumToInt(instructions.Addi.Mode.addi),
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.imm = @truncate(i12, split.low12),
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.rs1 = reg.id(),
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.rd = reg.id(),
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});
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), addi);
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// TODO: add test case for 32-bit immediate
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.lui(reg, hi20).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.addi(reg, reg, lo12).toU32());
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return;
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}
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// li rd, immediate
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@ -1764,14 +1727,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// If the type is a pointer, it means the pointer address is at this memory location.
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try self.genSetReg(src, reg, .{ .immediate = addr });
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const ld = @bitCast(u32, instructions.Load{
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.mode = @enumToInt(instructions.Load.Mode.ld),
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.rs1 = reg.id(),
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.rd = reg.id(),
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.offset = 0,
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});
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), ld);
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ld(reg, 0, reg).toU32());
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// LOAD imm=[i12 offset = 0], rs1 =
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// return self.fail("TODO implement genSetReg memory for riscv64");
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@ -1,50 +1,387 @@
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const std = @import("std");
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const DW = std.dwarf;
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pub const instructions = struct {
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pub const CallBreak = packed struct {
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pub const Mode = packed enum(u12) { ecall, ebreak };
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opcode: u7 = 0b1110011,
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unused1: u5 = 0,
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unused2: u3 = 0,
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unused3: u5 = 0,
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mode: u12, //: Mode
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};
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// I-type
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pub const Addi = packed struct {
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pub const Mode = packed enum(u3) { addi = 0b000, slti = 0b010, sltiu = 0b011, xori = 0b100, ori = 0b110, andi = 0b111 };
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opcode: u7 = 0b0010011,
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// TODO: this is only tagged to facilitate the monstrosity.
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// Once packed structs work make it packed.
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pub const Instruction = union(enum) {
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R: packed struct {
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opcode: u7,
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rd: u5,
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mode: u3, //: Mode
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funct3: u3,
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rs1: u5,
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imm: i12,
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};
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pub const Lui = packed struct {
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opcode: u7 = 0b0110111,
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rs2: u5,
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funct7: u7,
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},
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I: packed struct {
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opcode: u7,
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rd: u5,
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imm: i20,
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};
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// I_type
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pub const Load = packed struct {
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pub const Mode = packed enum(u3) { ld = 0b011, lwu = 0b110 };
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opcode: u7 = 0b0000011,
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rd: u5,
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mode: u3, //: Mode
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funct3: u3,
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rs1: u5,
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offset: i12,
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};
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// I-type
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pub const Jalr = packed struct {
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opcode: u7 = 0b1100111,
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rd: u5,
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mode: u3 = 0,
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imm0_11: u12,
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},
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S: packed struct {
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opcode: u7,
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imm0_4: u5,
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funct3: u3,
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rs1: u5,
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offset: i12,
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};
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rs2: u5,
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imm5_11: u7,
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},
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B: packed struct {
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opcode: u7,
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imm11: u1,
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imm1_4: u4,
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funct3: u3,
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rs1: u5,
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rs2: u5,
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imm5_10: u6,
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imm12: u1,
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},
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U: packed struct {
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opcode: u7,
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rd: u5,
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imm12_31: u20,
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},
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J: packed struct {
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opcode: u7,
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rd: u5,
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imm12_19: u8,
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imm11: u1,
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imm1_10: u10,
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imm20: u1,
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},
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// TODO: once packed structs work we can remove this monstrosity.
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.R => |v| @bitCast(u32, v),
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.I => |v| @bitCast(u32, v),
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.S => |v| @bitCast(u32, v),
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.B => |v| @intCast(u32, v.opcode) + (@intCast(u32, v.imm11) << 7) + (@intCast(u32, v.imm1_4) << 8) + (@intCast(u32, v.funct3) << 12) + (@intCast(u32, v.rs1) << 15) + (@intCast(u32, v.rs2) << 20) + (@intCast(u32, v.imm5_10) << 25) + (@intCast(u32, v.imm12) << 31),
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.U => |v| @bitCast(u32, v),
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.J => |v| @bitCast(u32, v),
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};
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}
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fn rType(op: u7, fn3: u3, fn7: u7, rd: Register, r1: Register, r2: Register) Instruction {
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return Instruction{
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.R = .{
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.opcode = op,
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.funct3 = fn3,
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.funct7 = fn7,
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.rd = @enumToInt(rd),
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.rs1 = @enumToInt(r1),
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.rs2 = @enumToInt(r2),
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},
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};
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}
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// RISC-V is all signed all the time -- convert immediates to unsigned for processing
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fn iType(op: u7, fn3: u3, rd: Register, r1: Register, imm: i12) Instruction {
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const umm = @bitCast(u12, imm);
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return Instruction{
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.I = .{
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.opcode = op,
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.funct3 = fn3,
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.rd = @enumToInt(rd),
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.rs1 = @enumToInt(r1),
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.imm0_11 = umm,
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},
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};
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}
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fn sType(op: u7, fn3: u3, r1: Register, r2: Register, imm: i12) Instruction {
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const umm = @bitCast(u12, imm);
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return Instruction{
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.S = .{
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.opcode = op,
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.funct3 = fn3,
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.rs1 = @enumToInt(r1),
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.rs2 = @enumToInt(r2),
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.imm0_4 = @truncate(u5, umm),
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.imm5_11 = @truncate(u7, umm >> 5),
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},
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};
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}
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// Use significance value rather than bit value, same for J-type
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// -- less burden on callsite, bonus semantic checking
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fn bType(op: u7, fn3: u3, r1: Register, r2: Register, imm: i13) Instruction {
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const umm = @bitCast(u13, imm);
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if (umm % 2 != 0) @panic("Internal error: misaligned branch target");
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return Instruction{
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.B = .{
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.opcode = op,
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.funct3 = fn3,
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.rs1 = @enumToInt(r1),
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.rs2 = @enumToInt(r2),
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.imm1_4 = @truncate(u4, umm >> 1),
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.imm5_10 = @truncate(u6, umm >> 5),
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.imm11 = @truncate(u1, umm >> 11),
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.imm12 = @truncate(u1, umm >> 12),
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},
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};
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}
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// We have to extract the 20 bits anyway -- let's not make it more painful
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fn uType(op: u7, rd: Register, imm: i20) Instruction {
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const umm = @bitCast(u20, imm);
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return Instruction{
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.U = .{
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.opcode = op,
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.rd = @enumToInt(rd),
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.imm12_31 = umm,
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},
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};
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}
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fn jType(op: u7, rd: Register, imm: i21) Instruction {
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const umm = @bitcast(u21, imm);
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if (umm % 2 != 0) @panic("Internal error: misaligned jump target");
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return Instruction{
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.J = .{
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.opcode = op,
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.rd = @enumToInt(rd),
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.imm1_10 = @truncate(u10, umm >> 1),
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.imm11 = @truncate(u1, umm >> 1),
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.imm12_19 = @truncate(u8, umm >> 12),
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.imm20 = @truncate(u1, umm >> 20),
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},
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};
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}
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// The meat and potatoes. Arguments are in the order in which they would appear in assembly code.
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// Arithmetic/Logical, Register-Register
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pub fn add(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b000, 0b0000000, rd, r1, r2);
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}
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pub fn sub(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b000, 0b0100000, rd, r1, r2);
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}
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pub fn @"and"(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b111, 0b0000000, rd, r1, r2);
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}
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pub fn @"or"(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b110, 0b0000000, rd, r1, r2);
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}
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pub fn xor(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b100, 0b0000000, rd, r1, r2);
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}
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pub fn sll(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b001, 0b0000000, rd, r1, r2);
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}
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pub fn srl(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b101, 0b0000000, rd, r1, r2);
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}
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pub fn sra(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b101, 0b0100000, rd, r1, r2);
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}
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pub fn slt(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b010, 0b0000000, rd, r1, r2);
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}
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pub fn sltu(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b011, 0b0000000, rd, r1, r2);
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}
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// Arithmetic/Logical, Register-Register (32-bit)
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pub fn addw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b000, rd, r1, r2);
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}
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pub fn subw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b000, 0b0100000, rd, r1, r2);
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}
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pub fn sllw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b001, 0b0000000, rd, r1, r2);
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}
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pub fn srlw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b101, 0b0000000, rd, r1, r2);
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}
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pub fn sraw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b101, 0b0100000, rd, r1, r2);
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}
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// Arithmetic/Logical, Register-Immediate
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pub fn addi(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b000, rd, r1, imm);
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}
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pub fn andi(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b111, rd, r1, imm);
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}
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pub fn ori(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b110, rd, r1, imm);
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}
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pub fn xori(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b100, rd, r1, imm);
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}
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pub fn slli(rd: Register, r1: Register, shamt: u6) Instruction {
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return iType(0b0010011, 0b001, rd, r1, shamt);
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}
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pub fn srli(rd: Register, r1: Register, shamt: u6) Instruction {
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return iType(0b0010011, 0b101, rd, r1, shamt);
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}
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pub fn srai(rd: Register, r1: Register, shamt: u6) Instruction {
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return iType(0b0010011, 0b101, rd, r1, (1 << 10) + shamt);
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}
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pub fn slti(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b010, rd, r1, imm);
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}
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pub fn sltiu(rd: Register, r1: Register, imm: u12) Instruction {
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return iType(0b0010011, 0b011, rd, r1, @bitCast(i12, imm));
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}
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|
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// Arithmetic/Logical, Register-Immediate (32-bit)
|
||||
|
||||
pub fn addiw(rd: Register, r1: Register, imm: i12) Instruction {
|
||||
return iType(0b0011011, 0b000, rd, r1, imm);
|
||||
}
|
||||
|
||||
pub fn slliw(rd: Register, r1: Register, shamt: u5) Instruction {
|
||||
return iType(0b0011011, 0b001, rd, r1, shamt);
|
||||
}
|
||||
|
||||
pub fn srliw(rd: Register, r1: Register, shamt: u5) Instruction {
|
||||
return iType(0b0011011, 0b101, rd, r1, shamt);
|
||||
}
|
||||
|
||||
pub fn sraiw(rd: Register, r1: Register, shamt: u5) Instruction {
|
||||
return iType(0b0011011, 0b101, rd, r1, (1 << 10) + shamt);
|
||||
}
|
||||
|
||||
// Upper Immediate
|
||||
|
||||
pub fn lui(rd: Register, imm: i20) Instruction {
|
||||
return uType(0b0110111, rd, imm);
|
||||
}
|
||||
|
||||
pub fn auipc(rd: Register, imm: i20) Instruction {
|
||||
return uType(0b0010111, rd, imm);
|
||||
}
|
||||
|
||||
// Load
|
||||
|
||||
pub fn ld(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b011, rd, base, offset);
|
||||
}
|
||||
|
||||
pub fn lw(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b010, rd, base, offset);
|
||||
}
|
||||
|
||||
pub fn lwu(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b110, rd, base, offset);
|
||||
}
|
||||
|
||||
pub fn lh(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b001, rd, base, offset);
|
||||
}
|
||||
|
||||
pub fn lhu(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b101, rd, base, offset);
|
||||
}
|
||||
|
||||
pub fn lb(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b000, rd, base, offset);
|
||||
}
|
||||
|
||||
pub fn lbu(rd: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b0000011, 0b100, rd, base, offset);
|
||||
}
|
||||
|
||||
// Store
|
||||
|
||||
pub fn sd(rs: Register, offset: i12, base: Register) Instruction {
|
||||
return sType(0b0100011, 0b011, base, rs, offset);
|
||||
}
|
||||
|
||||
pub fn sw(rs: Register, offset: i12, base: Register) Instruction {
|
||||
return sType(0b0100011, 0b010, base, rs, offset);
|
||||
}
|
||||
|
||||
pub fn sh(rs: Register, offset: i12, base: Register) Instruction {
|
||||
return sType(0b0100011, 0b001, base, rs, offset);
|
||||
}
|
||||
|
||||
pub fn sb(rs: Register, offset: i12, base: Register) Instruction {
|
||||
return sType(0b0100011, 0b000, base, rs, offset);
|
||||
}
|
||||
|
||||
// Fence
|
||||
// TODO: implement fence
|
||||
|
||||
// Branch
|
||||
|
||||
pub fn beq(r1: Register, r2: Register, offset: u13) Instruction {
|
||||
return bType(0b1100011, 0b000, r1, r2, offset);
|
||||
}
|
||||
|
||||
pub fn bne(r1: Register, r2: Register, offset: u13) Instruction {
|
||||
return bType(0b1100011, 0b001, r1, r2, offset);
|
||||
}
|
||||
|
||||
pub fn blt(r1: Register, r2: Register, offset: u13) Instruction {
|
||||
return bType(0b1100011, 0b100, r1, r2, offset);
|
||||
}
|
||||
|
||||
pub fn bge(r1: Register, r2: Register, offset: u13) Instruction {
|
||||
return bType(0b1100011, 0b101, r1, r2, offset);
|
||||
}
|
||||
|
||||
pub fn bltu(r1: Register, r2: Register, offset: u13) Instruction {
|
||||
return bType(0b1100011, 0b110, r1, r2, offset);
|
||||
}
|
||||
|
||||
pub fn bgeu(r1: Register, r2: Register, offset: u13) Instruction {
|
||||
return bType(0b1100011, 0b111, r1, r2, offset);
|
||||
}
|
||||
|
||||
// Jump
|
||||
|
||||
pub fn jal(link: Register, offset: i21) Instruction {
|
||||
return jType(0b1101111, link, offset);
|
||||
}
|
||||
|
||||
pub fn jalr(link: Register, offset: i12, base: Register) Instruction {
|
||||
return iType(0b1100111, 0b000, link, base, offset);
|
||||
}
|
||||
|
||||
// System
|
||||
|
||||
pub const ecall = iType(0b1110011, 0b000, .zero, .zero, 0x000);
|
||||
pub const ebreak = iType(0b1110011, 0b000, .zero, .zero, 0x001);
|
||||
};
|
||||
|
||||
// zig fmt: off
|
||||
pub const RawRegister = enum(u8) {
|
||||
pub const RawRegister = enum(u5) {
|
||||
x0, x1, x2, x3, x4, x5, x6, x7,
|
||||
x8, x9, x10, x11, x12, x13, x14, x15,
|
||||
x16, x17, x18, x19, x20, x21, x22, x23,
|
||||
@ -55,7 +392,7 @@ pub const RawRegister = enum(u8) {
|
||||
}
|
||||
};
|
||||
|
||||
pub const Register = enum(u8) {
|
||||
pub const Register = enum(u5) {
|
||||
// 64 bit registers
|
||||
zero, // zero
|
||||
ra, // return address. caller saved
|
||||
@ -76,11 +413,6 @@ pub const Register = enum(u8) {
|
||||
return null;
|
||||
}
|
||||
|
||||
/// Returns the register's id.
|
||||
pub fn id(self: @This()) u5 {
|
||||
return @truncate(u5, @enumToInt(self));
|
||||
}
|
||||
|
||||
/// Returns the index into `callee_preserved_regs`.
|
||||
pub fn allocIndex(self: Register) ?u4 {
|
||||
inline for(callee_preserved_regs) |cpreg, i| {
|
||||
@ -90,7 +422,7 @@ pub const Register = enum(u8) {
|
||||
}
|
||||
|
||||
pub fn dwarfLocOp(reg: Register) u8 {
|
||||
return @enumToInt(reg) + DW.OP_reg0;
|
||||
return @as(u8, @enumToInt(reg)) + DW.OP_reg0;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user