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stage2 x86_64 codegen: don't count return registers as callee-preserved

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Jacob G-W 2021-11-12 18:10:13 -05:00 committed by Jakub Konka
parent 6cf8a49bb0
commit f950d763a1
2 changed files with 11 additions and 12 deletions
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4
src/arch/x86_64/CodeGen.zig
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@ -1902,10 +1902,10 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
try self.register_manager.getReg(reg, null);
try self.genSetReg(arg_ty, reg, arg_mcv);
},
.stack_offset => {
.stack_offset => |off| {
// Here we need to emit instructions like this:
// mov qword ptr [rsp + stack_offset], x
return self.fail("TODO implement calling with parameters in memory", .{});
try self.genSetStack(arg_ty, off, arg_mcv);
},
.ptr_stack_offset => {
return self.fail("TODO implement calling with MCValue.ptr_stack_offset arg", .{});

19
src/arch/x86_64/bits.zig
View File

@ -84,15 +84,13 @@ pub const Register = enum(u7) {
/// Returns the index into `callee_preserved_regs`.
pub fn allocIndex(self: Register) ?u4 {
return switch (self) {
.rax, .eax, .ax, .al => 0,
.rcx, .ecx, .cx, .cl => 1,
.rdx, .edx, .dx, .dl => 2,
.rsi, .esi, .si => 3,
.rdi, .edi, .di => 4,
.r8, .r8d, .r8w, .r8b => 5,
.r9, .r9d, .r9w, .r9b => 6,
.r10, .r10d, .r10w, .r10b => 7,
.r11, .r11d, .r11w, .r11b => 8,
.rcx, .ecx, .cx, .cl => 0,
.rsi, .esi, .si => 1,
.rdi, .edi, .di => 2,
.r8, .r8d, .r8w, .r8b => 3,
.r9, .r9d, .r9w, .r9b => 4,
.r10, .r10d, .r10w, .r10b => 5,
.r11, .r11d, .r11w, .r11b => 6,
else => null,
};
}
@ -145,7 +143,8 @@ pub const Register = enum(u7) {
// zig fmt: on
/// These registers belong to the called function.
pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11 };
/// TODO should the return_regs be in this array?
pub const callee_preserved_regs = [_]Register{ .rcx, .rsi, .rdi, .r8, .r9, .r10, .r11 };
pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };