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x86_64: implement @floor, @ceil, and @trunc for float vectors
This commit is contained in:
Jacob Young
parent
057139fda5
commit
f8708e2c4d
@ -1587,9 +1587,9 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.round,
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=> try self.airUnaryMath(inst),
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.floor => try self.airRound(inst, Immediate.u(0b1_0_01)),
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.ceil => try self.airRound(inst, Immediate.u(0b1_0_10)),
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.trunc_float => try self.airRound(inst, Immediate.u(0b1_0_11)),
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.floor => try self.airRound(inst, 0b1_0_01),
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.ceil => try self.airRound(inst, 0b1_0_10),
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.trunc_float => try self.airRound(inst, 0b1_0_11),
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.sqrt => try self.airSqrt(inst),
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.neg, .fabs => try self.airFloatSign(inst),
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@ -4509,51 +4509,93 @@ fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
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}
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fn airRound(self: *Self, inst: Air.Inst.Index, mode: Immediate) !void {
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fn airRound(self: *Self, inst: Air.Inst.Index, mode: u4) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const ty = self.air.typeOf(un_op);
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if (!self.hasFeature(.sse4_1))
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return self.fail("TODO implement airRound without sse4_1 feature", .{});
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const src_mcv = try self.resolveInst(un_op);
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const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
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src_mcv
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else
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try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
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const mir_tag: Mir.Inst.Tag = switch (ty.zigTypeTag()) {
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.Float => switch (ty.floatBits(self.target.*)) {
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32 => .roundss,
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64 => .roundsd,
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else => return self.fail("TODO implement airRound for {}", .{
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ty.fmt(self.bin_file.options.module.?),
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}),
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},
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else => return self.fail("TODO implement airRound for {}", .{
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ty.fmt(self.bin_file.options.module.?),
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}),
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};
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assert(dst_mcv.isRegister());
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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const dst_reg = registerAlias(dst_mcv.getReg().?, abi_size);
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if (src_mcv.isRegister())
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try self.asmRegisterRegisterImmediate(
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mir_tag,
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dst_reg,
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registerAlias(src_mcv.getReg().?, abi_size),
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mode,
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)
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else
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try self.asmRegisterMemoryImmediate(
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mir_tag,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(@intCast(u32, ty.abiSize(self.target.*)))),
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mode,
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);
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const dst_reg = dst_mcv.getReg().?;
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const dst_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genRound(ty, dst_reg, src_mcv, mode);
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return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
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}
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fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: u4) !void {
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if (!self.hasFeature(.sse4_1))
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return self.fail("TODO implement genRound without sse4_1 feature", .{});
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const mir_tag = if (@as(?Mir.Inst.Tag, switch (ty.zigTypeTag()) {
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.Float => switch (ty.floatBits(self.target.*)) {
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32 => if (self.hasFeature(.avx)) .vroundss else .roundss,
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64 => if (self.hasFeature(.avx)) .vroundsd else .roundsd,
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16, 80, 128 => null,
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else => unreachable,
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},
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.Vector => switch (ty.childType().zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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32 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vroundss else .roundss,
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2...4 => if (self.hasFeature(.avx)) .vroundps else .roundps,
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5...8 => if (self.hasFeature(.avx)) .vroundps else null,
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else => null,
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},
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64 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vroundsd else .roundsd,
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2 => if (self.hasFeature(.avx)) .vroundpd else .roundpd,
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3...4 => if (self.hasFeature(.avx)) .vroundpd else null,
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else => null,
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},
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16, 80, 128 => null,
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else => unreachable,
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},
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else => null,
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},
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else => unreachable,
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})) |tag| tag else return self.fail("TODO implement genRound for {}", .{
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ty.fmt(self.bin_file.options.module.?),
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});
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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const dst_alias = registerAlias(dst_reg, abi_size);
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switch (mir_tag) {
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.vroundss, .vroundsd => if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
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mir_tag,
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dst_alias,
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dst_alias,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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Immediate.u(mode),
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) else try self.asmRegisterRegisterRegisterImmediate(
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mir_tag,
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dst_alias,
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dst_alias,
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registerAlias(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, src_mcv), abi_size),
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Immediate.u(mode),
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),
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else => if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate(
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mir_tag,
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dst_alias,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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Immediate.u(mode),
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) else try self.asmRegisterRegisterImmediate(
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mir_tag,
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dst_alias,
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registerAlias(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, src_mcv), abi_size),
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Immediate.u(mode),
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),
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}
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}
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fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const ty = self.air.typeOf(un_op);
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@ -6188,18 +6230,18 @@ fn genBinOp(
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})) |tag| tag else return self.fail("TODO implement genBinOp for {s} {}", .{
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@tagName(air_tag), lhs_ty.fmt(self.bin_file.options.module.?),
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});
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const dst_alias = registerAlias(dst_mcv.getReg().?, abi_size);
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const dst_reg = registerAlias(dst_mcv.getReg().?, abi_size);
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if (self.hasFeature(.avx)) {
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const src1_alias =
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if (copied_to_dst) dst_alias else registerAlias(lhs_mcv.getReg().?, abi_size);
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if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size);
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if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
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mir_tag,
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dst_alias,
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dst_reg,
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src1_alias,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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) else try self.asmRegisterRegisterRegister(
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mir_tag,
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dst_alias,
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dst_reg,
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src1_alias,
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registerAlias(if (src_mcv.isRegister())
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src_mcv.getReg().?
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@ -6210,11 +6252,11 @@ fn genBinOp(
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assert(copied_to_dst);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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mir_tag,
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dst_alias,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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) else try self.asmRegisterRegister(
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mir_tag,
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dst_alias,
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dst_reg,
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registerAlias(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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@ -6223,60 +6265,16 @@ fn genBinOp(
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}
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switch (air_tag) {
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.add, .sub, .mul, .div_float, .div_exact => {},
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.div_trunc, .div_floor => if (self.hasFeature(.sse4_1)) {
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const round_tag = if (@as(?Mir.Inst.Tag, switch (lhs_ty.zigTypeTag()) {
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.Float => switch (lhs_ty.floatBits(self.target.*)) {
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32 => if (self.hasFeature(.avx)) .vroundss else .roundss,
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64 => if (self.hasFeature(.avx)) .vroundsd else .roundsd,
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16, 80, 128 => null,
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else => unreachable,
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},
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.Vector => switch (lhs_ty.childType().zigTypeTag()) {
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.Float => switch (lhs_ty.childType().floatBits(self.target.*)) {
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32 => switch (lhs_ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vroundss else .roundss,
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2...4 => if (self.hasFeature(.avx)) .vroundps else .roundps,
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5...8 => if (self.hasFeature(.avx)) .vroundps else null,
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else => null,
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},
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64 => switch (lhs_ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vroundsd else .roundsd,
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2 => if (self.hasFeature(.avx)) .vroundpd else .roundpd,
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3...4 => if (self.hasFeature(.avx)) .vroundpd else null,
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else => null,
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},
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16, 80, 128 => null,
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else => unreachable,
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},
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else => null,
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},
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else => unreachable,
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})) |tag| tag else return self.fail("TODO implement genBinOp for {s} {}", .{
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@tagName(air_tag), lhs_ty.fmt(self.bin_file.options.module.?),
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});
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const round_mode = Immediate.u(switch (air_tag) {
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.div_trunc, .div_floor => try self.genRound(
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lhs_ty,
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dst_reg,
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.{ .register = dst_reg },
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switch (air_tag) {
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.div_trunc => 0b1_0_11,
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.div_floor => 0b1_0_01,
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else => unreachable,
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});
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switch (round_tag) {
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.vroundss, .vroundsd => try self.asmRegisterRegisterRegisterImmediate(
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round_tag,
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dst_alias,
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dst_alias,
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dst_alias,
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round_mode,
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),
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else => try self.asmRegisterRegisterImmediate(
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round_tag,
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dst_alias,
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dst_alias,
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round_mode,
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),
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}
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} else return self.fail("TODO implement genBinOp for {s} {} without sse4_1", .{
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@tagName(air_tag), lhs_ty.fmt(self.bin_file.options.module.?),
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}),
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},
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),
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.max, .min => {}, // TODO: unordered select
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else => unreachable,
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}
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@ -617,7 +617,8 @@ fn testFloor() !void {
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test "@floor with vectors" {
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64 and
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!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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@ -707,7 +708,8 @@ fn testCeil() !void {
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test "@ceil with vectors" {
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64 and
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!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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@ -797,7 +799,8 @@ fn testTrunc() !void {
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test "@trunc with vectors" {
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64 and
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!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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