From f7ade7e63bfe63258807df6a97e222072cde1a35 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= <xq@random-projects.net>
Date: Tue, 10 Jan 2023 09:39:56 +0100
Subject: [PATCH] Fixes bug in AVR codegen for llvm backend

---
 src/codegen/llvm.zig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 39bb0dd94c..bca116f18f 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -4213,6 +4213,7 @@ pub const DeclGen = struct {
         // verbatim, and the result should test as non-null.
         const target = dg.module.getTarget();
         const int = switch (target.cpu.arch.ptrBitWidth()) {
+            16 => llvm_usize.constInt(0xaaaa, .False),
             32 => llvm_usize.constInt(0xaaaaaaaa, .False),
             64 => llvm_usize.constInt(0xaaaaaaaa_aaaaaaaa, .False),
             else => unreachable,