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x86_64: implement a more generic assembler for inline assembly
This commit is contained in:
Jacob Young
Jakub Konka
parent
a329450aa4
commit
f5f0d95f0e
@ -28,10 +28,11 @@ const Type = @import("../../type.zig").Type;
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const TypedValue = @import("../../TypedValue.zig");
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const Value = @import("../../value.zig").Value;
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const bits = @import("bits.zig");
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const abi = @import("abi.zig");
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const errUnionPayloadOffset = codegen.errUnionPayloadOffset;
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const bits = @import("bits.zig");
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const encoder = @import("encoder.zig");
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const errUnionErrorOffset = codegen.errUnionErrorOffset;
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const errUnionPayloadOffset = codegen.errUnionPayloadOffset;
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const Condition = bits.Condition;
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const Immediate = bits.Immediate;
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@ -6570,7 +6571,8 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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return self.fail("unrecognized constraint: '{s}'", .{constraint});
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args.putAssumeCapacity(name, mcv);
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switch (mcv) {
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.register => |reg| _ = self.register_manager.lockRegAssumeUnused(reg),
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.register => |reg| _ = if (RegisterManager.indexOfRegIntoTracked(reg)) |_|
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self.register_manager.lockRegAssumeUnused(reg),
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else => {},
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}
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if (output == .none) result = mcv;
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@ -6609,70 +6611,139 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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}
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const asm_source = mem.sliceAsBytes(self.air.extra[extra_i..])[0..extra.data.source_len];
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var line_it = mem.tokenize(u8, asm_source, "\n\r");
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var line_it = mem.tokenize(u8, asm_source, "\n\r;");
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while (line_it.next()) |line| {
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var mnem_it = mem.tokenize(u8, line, " \t");
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const mnem = mnem_it.next() orelse continue;
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if (mem.startsWith(u8, mnem, "#")) continue;
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var arg_it = mem.tokenize(u8, mnem_it.rest(), ", ");
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if (std.ascii.eqlIgnoreCase(mnem, "syscall")) {
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if (arg_it.next()) |trailing| if (!mem.startsWith(u8, trailing, "#"))
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return self.fail("Too many operands: '{s}'", .{line});
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try self.asmOpOnly(.syscall);
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} else if (std.ascii.eqlIgnoreCase(mnem, "push")) {
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const src = arg_it.next() orelse
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return self.fail("Not enough operands: '{s}'", .{line});
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if (arg_it.next()) |trailing| if (!mem.startsWith(u8, trailing, "#"))
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return self.fail("Too many operands: '{s}'", .{line});
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if (mem.startsWith(u8, src, "$")) {
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const imm = std.fmt.parseInt(u32, src["$".len..], 0) catch
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return self.fail("Invalid immediate: '{s}'", .{src});
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try self.asmImmediate(.push, Immediate.u(imm));
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} else if (mem.startsWith(u8, src, "%%")) {
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const reg = parseRegName(src["%%".len..]) orelse
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return self.fail("Invalid register: '{s}'", .{src});
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try self.asmRegister(.push, reg);
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} else return self.fail("Unsupported operand: '{s}'", .{src});
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} else if (std.ascii.eqlIgnoreCase(mnem, "pop")) {
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const dst = arg_it.next() orelse
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return self.fail("Not enough operands: '{s}'", .{line});
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if (arg_it.next()) |trailing| if (!mem.startsWith(u8, trailing, "#"))
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return self.fail("Too many operands: '{s}'", .{line});
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if (mem.startsWith(u8, dst, "%%")) {
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const reg = parseRegName(dst["%%".len..]) orelse
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return self.fail("Invalid register: '{s}'", .{dst});
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try self.asmRegister(.pop, reg);
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} else return self.fail("Unsupported operand: '{s}'", .{dst});
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} else if (std.ascii.eqlIgnoreCase(mnem, "movq")) {
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const src = arg_it.next() orelse
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return self.fail("Not enough operands: '{s}'", .{line});
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const dst = arg_it.next() orelse
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return self.fail("Not enough operands: '{s}'", .{line});
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if (arg_it.next()) |trailing| if (!mem.startsWith(u8, trailing, "#"))
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return self.fail("Too many operands: '{s}'", .{line});
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if (mem.startsWith(u8, src, "%%")) {
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const colon = mem.indexOfScalarPos(u8, src, "%%".len + 2, ':');
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const src_reg = parseRegName(src["%%".len .. colon orelse src.len]) orelse
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return self.fail("Invalid register: '{s}'", .{src});
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const mnem_str = mnem_it.next() orelse continue;
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if (mem.startsWith(u8, mnem_str, "#")) continue;
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const mnem_size: ?Memory.PtrSize = if (mem.endsWith(u8, mnem_str, "b"))
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.byte
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else if (mem.endsWith(u8, mnem_str, "w"))
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.word
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else if (mem.endsWith(u8, mnem_str, "l"))
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.dword
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else if (mem.endsWith(u8, mnem_str, "q"))
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.qword
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else
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null;
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const mnem = std.meta.stringToEnum(Mir.Inst.Tag, mnem_str) orelse
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(if (mnem_size) |_|
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std.meta.stringToEnum(Mir.Inst.Tag, mnem_str[0 .. mnem_str.len - 1])
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else
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null) orelse return self.fail("Invalid mnemonic: '{s}'", .{mnem_str});
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var op_it = mem.tokenize(u8, mnem_it.rest(), ",");
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var ops = [1]encoder.Instruction.Operand{.none} ** 4;
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for (&ops) |*op| {
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const op_str = mem.trim(u8, op_it.next() orelse break, " \t");
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if (mem.startsWith(u8, op_str, "#")) break;
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if (mem.startsWith(u8, op_str, "%%")) {
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const colon = mem.indexOfScalarPos(u8, op_str, "%%".len + 2, ':');
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const reg = parseRegName(op_str["%%".len .. colon orelse op_str.len]) orelse
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return self.fail("Invalid register: '{s}'", .{op_str});
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if (colon) |colon_pos| {
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const src_disp = std.fmt.parseInt(i32, src[colon_pos + 1 ..], 0) catch
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return self.fail("Invalid immediate: '{s}'", .{src});
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if (mem.startsWith(u8, dst, "%[") and mem.endsWith(u8, dst, "]")) {
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switch (args.get(dst["%[".len .. dst.len - "]".len]) orelse
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return self.fail("no matching constraint for: '{s}'", .{dst})) {
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.register => |dst_reg| try self.asmRegisterMemory(
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.mov,
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dst_reg,
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Memory.sib(.qword, .{ .base = src_reg, .disp = src_disp }),
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),
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else => return self.fail("Invalid constraint: '{s}'", .{dst}),
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}
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} else return self.fail("Unsupported operand: '{s}'", .{dst});
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} else return self.fail("Unsupported operand: '{s}'", .{src});
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}
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} else {
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return self.fail("Unsupported instruction: '{s}'", .{mnem});
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}
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const disp = std.fmt.parseInt(i32, op_str[colon_pos + 1 ..], 0) catch
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return self.fail("Invalid displacement: '{s}'", .{op_str});
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op.* = .{ .mem = Memory.sib(
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mnem_size orelse return self.fail("Unknown size: '{s}'", .{op_str}),
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.{ .base = reg, .disp = disp },
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) };
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} else {
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if (mnem_size) |size| if (reg.bitSize() != size.bitSize())
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return self.fail("Invalid register size: '{s}'", .{op_str});
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op.* = .{ .reg = reg };
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}
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} else if (mem.startsWith(u8, op_str, "%[") and mem.endsWith(u8, op_str, "]")) {
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switch (args.get(op_str["%[".len .. op_str.len - "]".len]) orelse
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return self.fail("No matching constraint: '{s}'", .{op_str})) {
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.register => |reg| op.* = .{ .reg = reg },
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else => return self.fail("Invalid constraint: '{s}'", .{op_str}),
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}
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} else if (mem.startsWith(u8, op_str, "$")) {
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if (std.fmt.parseInt(i32, op_str["$".len..], 0)) |s| {
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if (mnem_size) |size| {
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const max = @as(u64, std.math.maxInt(u64)) >>
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@intCast(u6, 64 - (size.bitSize() - 1));
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if ((if (s < 0) ~s else s) > max)
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return self.fail("Invalid immediate size: '{s}'", .{op_str});
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}
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op.* = .{ .imm = Immediate.s(s) };
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} else |_| if (std.fmt.parseInt(u64, op_str["$".len..], 0)) |u| {
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if (mnem_size) |size| {
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const max = @as(u64, std.math.maxInt(u64)) >>
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@intCast(u6, 64 - size.bitSize());
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if (u > max)
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return self.fail("Invalid immediate size: '{s}'", .{op_str});
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}
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op.* = .{ .imm = Immediate.u(u) };
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} else |_| return self.fail("Invalid immediate: '{s}'", .{op_str});
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} else return self.fail("Invalid operand: '{s}'", .{op_str});
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} else if (op_it.next()) |op_str| return self.fail("Extra operand: '{s}'", .{op_str});
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(switch (ops[0]) {
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.none => self.asmOpOnly(mnem),
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.reg => |reg0| switch (ops[1]) {
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.none => self.asmRegister(mnem, reg0),
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.reg => |reg1| switch (ops[2]) {
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.none => self.asmRegisterRegister(mnem, reg1, reg0),
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.reg => |reg2| switch (ops[3]) {
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.none => self.asmRegisterRegisterRegister(mnem, reg2, reg1, reg0),
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else => error.InvalidInstruction,
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},
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.mem => |mem2| switch (ops[3]) {
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.none => self.asmMemoryRegisterRegister(mnem, mem2, reg1, reg0),
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else => error.InvalidInstruction,
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},
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else => error.InvalidInstruction,
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},
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.mem => |mem1| switch (ops[2]) {
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.none => self.asmMemoryRegister(mnem, mem1, reg0),
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else => error.InvalidInstruction,
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},
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else => error.InvalidInstruction,
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},
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.mem => |mem0| switch (ops[1]) {
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.none => self.asmMemory(mnem, mem0),
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.reg => |reg1| switch (ops[2]) {
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.none => self.asmRegisterMemory(mnem, reg1, mem0),
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else => error.InvalidInstruction,
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},
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else => error.InvalidInstruction,
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},
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.imm => |imm0| switch (ops[1]) {
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.none => self.asmImmediate(mnem, imm0),
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.reg => |reg1| switch (ops[2]) {
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.none => self.asmRegisterImmediate(mnem, reg1, imm0),
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.reg => |reg2| switch (ops[3]) {
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.none => self.asmRegisterRegisterImmediate(mnem, reg2, reg1, imm0),
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else => error.InvalidInstruction,
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},
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.mem => |mem2| switch (ops[3]) {
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.none => self.asmMemoryRegisterImmediate(mnem, mem2, reg1, imm0),
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else => error.InvalidInstruction,
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},
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else => error.InvalidInstruction,
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},
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.mem => |mem1| switch (ops[2]) {
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.none => self.asmMemoryImmediate(mnem, mem1, imm0),
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else => error.InvalidInstruction,
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},
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else => error.InvalidInstruction,
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},
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}) catch |err| switch (err) {
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error.InvalidInstruction => return self.fail(
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"Invalid instruction: '{s} {s} {s} {s} {s}'",
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.{
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@tagName(mnem),
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@tagName(ops[0]),
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@tagName(ops[1]),
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@tagName(ops[2]),
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@tagName(ops[3]),
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},
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),
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else => |e| return e,
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};
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}
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}
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