diff --git a/src/codegen.zig b/src/codegen.zig
index 57fd732b42..c3cd64cf73 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -899,6 +899,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
                 .load => return self.genLoad(inst.castTag(.load).?),
                 .loop => return self.genLoop(inst.castTag(.loop).?),
                 .not => return self.genNot(inst.castTag(.not).?),
+                .mul => return self.genMul(inst.castTag(.mul).?),
                 .ptrtoint => return self.genPtrToInt(inst.castTag(.ptrtoint).?),
                 .ref => return self.genRef(inst.castTag(.ref).?),
                 .ret => return self.genRet(inst.castTag(.ret).?),
@@ -1128,6 +1129,16 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
             }
         }
 
+        fn genMul(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
+            // No side effects, so if it's unreferenced, do nothing.
+            if (inst.base.isUnused())
+                return MCValue.dead;
+            switch (arch) {
+                .arm, .armeb => return try self.genArmMul(&inst.base, inst.lhs, inst.rhs),
+                else => return self.fail(inst.base.src, "TODO implement mul for {}", .{self.target.cpu.arch}),
+            }
+        }
+
         fn genBitAnd(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
             // No side effects, so if it's unreferenced, do nothing.
             if (inst.base.isUnused())
@@ -1478,6 +1489,38 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
             }
         }
 
+        fn genArmMul(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst) !MCValue {
+            const lhs = try self.resolveInst(op_lhs);
+            const rhs = try self.resolveInst(op_rhs);
+
+            // Destination must be a register
+            // LHS must be a register
+            // RHS must be a register
+            var dst_mcv: MCValue = undefined;
+            var lhs_mcv: MCValue = undefined;
+            var rhs_mcv: MCValue = undefined;
+            if (self.reuseOperand(inst, 0, lhs)) {
+                // LHS is the destination
+                lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs;
+                rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
+                dst_mcv = lhs_mcv;
+            } else if (self.reuseOperand(inst, 1, rhs)) {
+                // RHS is the destination
+                lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs;
+                rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
+                dst_mcv = rhs_mcv;
+            } else {
+                // TODO save 1 copy instruction by directly allocating the destination register
+                // LHS is the destination
+                lhs_mcv = try self.copyToNewRegister(inst, lhs);
+                rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
+                dst_mcv = lhs_mcv;
+            }
+
+            writeInt(u32, try self.code.addManyAsArray(4), Instruction.mul(.al, dst_mcv.register, lhs_mcv.register, rhs_mcv.register).toU32());
+            return dst_mcv;
+        }
+
         /// ADD, SUB, XOR, OR, AND
         fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue {
             try self.code.ensureCapacity(self.code.items.len + 8);
diff --git a/src/ir.zig b/src/ir.zig
index eddc885d14..996f3b9782 100644
--- a/src/ir.zig
+++ b/src/ir.zig
@@ -106,6 +106,7 @@ pub const Inst = struct {
         store,
         sub,
         unreach,
+        mul,
         not,
         floatcast,
         intcast,
@@ -165,6 +166,7 @@ pub const Inst = struct {
 
                 .add,
                 .sub,
+                .mul,
                 .cmp_lt,
                 .cmp_lte,
                 .cmp_eq,
diff --git a/src/zir.zig b/src/zir.zig
index d013f25ee5..7a3a1e2684 100644
--- a/src/zir.zig
+++ b/src/zir.zig
@@ -1649,6 +1649,7 @@ const DumpTzir = struct {
 
                 .add,
                 .sub,
+                .mul,
                 .cmp_lt,
                 .cmp_lte,
                 .cmp_eq,
@@ -1771,6 +1772,7 @@ const DumpTzir = struct {
 
                 .add,
                 .sub,
+                .mul,
                 .cmp_lt,
                 .cmp_lte,
                 .cmp_eq,
diff --git a/src/zir_sema.zig b/src/zir_sema.zig
index 864f766f54..1cf550852f 100644
--- a/src/zir_sema.zig
+++ b/src/zir_sema.zig
@@ -2075,6 +2075,7 @@ fn zirArithmetic(mod: *Module, scope: *Scope, inst: *zir.Inst.BinOp) InnerError!
     const ir_tag = switch (inst.base.tag) {
         .add => Inst.Tag.add,
         .sub => Inst.Tag.sub,
+        .mul => Inst.Tag.mul,
         else => return mod.fail(scope, inst.base.src, "TODO implement arithmetic for operand '{s}''", .{@tagName(inst.base.tag)}),
     };
 
diff --git a/test/stage2/arm.zig b/test/stage2/arm.zig
index 06e359ccff..1bc3f23058 100644
--- a/test/stage2/arm.zig
+++ b/test/stage2/arm.zig
@@ -344,4 +344,38 @@ pub fn addCases(ctx: *TestContext) !void {
             "",
         );
     }
+
+    {
+        var case = ctx.exe("integer multiplication", linux_arm);
+        // Simple u32 integer multiplication
+        case.addCompareOutput(
+            \\export fn _start() noreturn {
+            \\    assert(mul(1, 1) == 1);
+            \\    assert(mul(42, 1) == 42);
+            \\    assert(mul(1, 42) == 42);
+            \\    assert(mul(123, 42) == 5166);
+            \\    exit();
+            \\}
+            \\
+            \\fn mul(x: u32, y: u32) u32 {
+            \\    return x * y;
+            \\}
+            \\
+            \\fn assert(ok: bool) void {
+            \\    if (!ok) unreachable;
+            \\}
+            \\
+            \\fn exit() noreturn {
+            \\    asm volatile ("svc #0"
+            \\        :
+            \\        : [number] "{r7}" (1),
+            \\          [arg1] "{r0}" (0)
+            \\        : "memory"
+            \\    );
+            \\    unreachable;
+            \\}
+        ,
+            "",
+        );
+    }
 }