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x86_64: implement 128-bit integer shifts in registers
This commit is contained in:
Jacob Young
parent
54e7f58fcb
commit
f28b1657aa
@ -6427,139 +6427,233 @@ fn genShiftBinOpMir(
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}),
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}
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} else if (abi_size <= 16) {
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const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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const info: struct { offsets: [2]i32, double_tag: Mir.Inst.FixedTag } = switch (tag[0]) {
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._l => .{ .offsets = .{ 0, 8 }, .double_tag = .{ ._ld, .sh } },
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._r => .{ .offsets = .{ 8, 0 }, .double_tag = .{ ._rd, .sh } },
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const info: struct { indices: [2]u31, double_tag: Mir.Inst.FixedTag } = switch (tag[0]) {
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._l => .{ .indices = .{ 0, 1 }, .double_tag = .{ ._ld, .sh } },
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._r => .{ .indices = .{ 1, 0 }, .double_tag = .{ ._rd, .sh } },
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else => unreachable,
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};
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switch (lhs_mcv) {
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.load_frame => |dst_frame_addr| switch (rhs_mcv) {
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.immediate => |rhs_imm| if (rhs_imm == 0) {} else if (rhs_imm < 64) {
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try self.asmRegisterMemory(
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.{ ._, .mov },
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tmp_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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);
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try self.asmMemoryRegisterImmediate(
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.register_pair => |lhs_regs| switch (rhs_mcv) {
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.immediate => |rhs_imm| if (rhs_imm > 0 and rhs_imm < 64) {
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try self.asmRegisterRegisterImmediate(
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info.double_tag,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[1],
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}),
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tmp_reg,
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lhs_regs[info.indices[1]],
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lhs_regs[info.indices[0]],
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Immediate.u(rhs_imm),
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);
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try self.asmMemoryImmediate(
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try self.asmRegisterImmediate(
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tag,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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lhs_regs[info.indices[0]],
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Immediate.u(rhs_imm),
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);
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} else {
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assert(rhs_imm < 128);
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try self.asmRegisterMemory(
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try self.asmRegisterRegister(
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.{ ._, .mov },
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tmp_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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lhs_regs[info.indices[1]],
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lhs_regs[info.indices[0]],
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);
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if (rhs_imm > 64) {
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try self.asmRegisterImmediate(tag, tmp_reg, Immediate.u(rhs_imm - 64));
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}
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[1],
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}),
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tmp_reg,
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);
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if (tag[0] == ._r and tag[1] == .sa) try self.asmMemoryImmediate(
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if (tag[0] == ._r and tag[1] == .sa) try self.asmRegisterImmediate(
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tag,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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lhs_regs[info.indices[0]],
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Immediate.u(63),
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) else {
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try self.asmRegisterRegister(.{ ._, .xor }, tmp_reg.to32(), tmp_reg.to32());
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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tmp_reg,
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);
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}
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) else try self.asmRegisterRegister(
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.{ ._, .xor },
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lhs_regs[info.indices[0]],
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lhs_regs[info.indices[0]],
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);
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if (rhs_imm > 64) try self.asmRegisterImmediate(
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tag,
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lhs_regs[info.indices[1]],
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Immediate.u(rhs_imm - 64),
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);
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},
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else => {
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const first_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const first_lock = self.register_manager.lockRegAssumeUnused(first_reg);
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defer self.register_manager.unlockReg(first_lock);
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.register => |rhs_reg| {
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const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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const second_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const second_lock = self.register_manager.lockRegAssumeUnused(second_reg);
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defer self.register_manager.unlockReg(second_lock);
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try self.genSetReg(.cl, Type.u8, rhs_mcv);
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try self.asmRegisterMemory(
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.{ ._, .mov },
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first_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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);
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try self.asmRegisterMemory(
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.{ ._, .mov },
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second_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[1],
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}),
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);
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if (tag[0] == ._r and tag[1] == .sa) {
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try self.asmRegisterRegister(.{ ._, .mov }, tmp_reg, first_reg);
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try self.asmRegisterRegister(.{ ._, .mov }, tmp_reg, lhs_regs[info.indices[0]]);
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try self.asmRegisterImmediate(tag, tmp_reg, Immediate.u(63));
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} else try self.asmRegisterRegister(
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.{ ._, .xor },
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tmp_reg.to32(),
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tmp_reg.to32(),
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);
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try self.asmRegisterRegisterRegister(info.double_tag, second_reg, first_reg, .cl);
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try self.asmRegisterRegister(tag, first_reg, .cl);
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try self.asmRegisterImmediate(.{ ._, .cmp }, .cl, Immediate.u(64));
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try self.asmCmovccRegisterRegister(second_reg, first_reg, .ae);
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try self.asmCmovccRegisterRegister(first_reg, tmp_reg, .ae);
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[1],
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}),
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second_reg,
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try self.asmRegisterRegisterRegister(
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info.double_tag,
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lhs_regs[info.indices[1]],
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lhs_regs[info.indices[0]],
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registerAlias(rhs_reg, 1),
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);
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.offsets[0],
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}),
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first_reg,
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try self.asmRegisterRegister(
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tag,
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lhs_regs[info.indices[0]],
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registerAlias(rhs_reg, 1),
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);
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try self.asmRegisterImmediate(
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.{ ._, .cmp },
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registerAlias(rhs_reg, 1),
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Immediate.u(64),
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);
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try self.asmCmovccRegisterRegister(
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lhs_regs[info.indices[1]],
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lhs_regs[info.indices[0]],
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.ae,
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);
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try self.asmCmovccRegisterRegister(lhs_regs[info.indices[0]], tmp_reg, .ae);
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},
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else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
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@tagName(lhs_mcv),
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@tagName(rhs_mcv),
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}),
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},
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.load_frame => |dst_frame_addr| {
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const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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switch (rhs_mcv) {
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.immediate => |rhs_imm| if (rhs_imm > 0 and rhs_imm < 64) {
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try self.asmRegisterMemory(
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.{ ._, .mov },
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tmp_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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);
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try self.asmMemoryRegisterImmediate(
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info.double_tag,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[1] * 8,
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}),
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tmp_reg,
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Immediate.u(rhs_imm),
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);
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try self.asmMemoryImmediate(
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tag,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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Immediate.u(rhs_imm),
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);
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} else {
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assert(rhs_imm < 128);
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try self.asmRegisterMemory(
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.{ ._, .mov },
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tmp_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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);
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if (rhs_imm > 64) try self.asmRegisterImmediate(
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tag,
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tmp_reg,
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Immediate.u(rhs_imm - 64),
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);
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[1] * 8,
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}),
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tmp_reg,
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);
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if (tag[0] == ._r and tag[1] == .sa) try self.asmMemoryImmediate(
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tag,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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Immediate.u(63),
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) else {
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try self.asmRegisterRegister(.{ ._, .xor }, tmp_reg.to32(), tmp_reg.to32());
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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tmp_reg,
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);
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}
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},
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.register => |rhs_reg| {
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const first_reg =
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try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const first_lock = self.register_manager.lockRegAssumeUnused(first_reg);
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defer self.register_manager.unlockReg(first_lock);
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const second_reg =
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try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const second_lock = self.register_manager.lockRegAssumeUnused(second_reg);
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defer self.register_manager.unlockReg(second_lock);
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try self.asmRegisterMemory(
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.{ ._, .mov },
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first_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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);
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try self.asmRegisterMemory(
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.{ ._, .mov },
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second_reg,
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[1] * 8,
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}),
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);
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if (tag[0] == ._r and tag[1] == .sa) {
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try self.asmRegisterRegister(.{ ._, .mov }, tmp_reg, first_reg);
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try self.asmRegisterImmediate(tag, tmp_reg, Immediate.u(63));
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} else try self.asmRegisterRegister(
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.{ ._, .xor },
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tmp_reg.to32(),
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tmp_reg.to32(),
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);
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try self.asmRegisterRegisterRegister(
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info.double_tag,
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second_reg,
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first_reg,
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registerAlias(rhs_reg, 1),
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);
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try self.asmRegisterRegister(tag, first_reg, registerAlias(rhs_reg, 1));
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try self.asmRegisterImmediate(
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.{ ._, .cmp },
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registerAlias(rhs_reg, 1),
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Immediate.u(64),
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);
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try self.asmCmovccRegisterRegister(second_reg, first_reg, .ae);
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try self.asmCmovccRegisterRegister(first_reg, tmp_reg, .ae);
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[1] * 8,
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}),
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second_reg,
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);
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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.base = .{ .frame = dst_frame_addr.index },
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.disp = dst_frame_addr.off + info.indices[0] * 8,
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}),
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first_reg,
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);
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},
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else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
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@tagName(lhs_mcv),
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@tagName(rhs_mcv),
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}),
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}
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},
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else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
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@tagName(lhs_mcv),
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