From f1e0c35db4167b8cc5a70d2270028287e737fff4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:10:07 +0200 Subject: [PATCH] std.Target: Remove `hsail`/`hsail64` arch tags. This seems to just be dead. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project%20hsail&type=code See: https://github.com/HSAFoundation/HSAIL-Tools/commits/master --- lib/compiler/aro/aro/target.zig | 6 ------ lib/std/Target.zig | 16 ---------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 34 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 8d51fbabfd..82dc3af430 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .x86, .xcore, .nvptx, - .hsail, .spir, .kalimba, .shave, @@ -497,7 +496,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .aarch64_be => copy.cpu.arch = .armeb, .nvptx64 => copy.cpu.arch = .nvptx, .wasm64 => copy.cpu.arch = .wasm32, - .hsail64 => copy.cpu.arch = .hsail, .spir64 => copy.cpu.arch = .spir, .spirv64 => copy.cpu.arch = .spirv32, .loongarch64 => copy.cpu.arch = .loongarch32, @@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .bpfel, .nvptx64, .wasm64, - .hsail64, .spir64, .spirv64, .loongarch64, @@ -558,7 +555,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .aarch64_32 => copy.cpu.arch = .aarch64, .arm => copy.cpu.arch = .aarch64, .armeb => copy.cpu.arch = .aarch64_be, - .hsail => copy.cpu.arch = .hsail64, .loongarch32 => copy.cpu.arch = .loongarch64, .mips => copy.cpu.arch = .mips64, .mipsel => copy.cpu.arch = .mips64el, @@ -627,8 +623,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .hsail => "hsail", - .hsail64 => "hsail64", .spir => "spir", .spir64 => "spir64", .spirv32 => "spirv32", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index fedd339b3d..c69a730b2e 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1011,8 +1011,6 @@ pub const Cpu = struct { xtensa, nvptx, nvptx64, - hsail, - hsail64, spir, spir64, spirv, @@ -1154,7 +1152,6 @@ pub const Cpu = struct { .xcore => .XCORE, .xtensa => .XTENSA, .nvptx => .NONE, - .hsail => .NONE, .spir => .NONE, .kalimba => .CSR_KALIMBA, .shave => .NONE, @@ -1170,7 +1167,6 @@ pub const Cpu = struct { .riscv64 => .RISCV, .x86_64 => .X86_64, .nvptx64 => .NONE, - .hsail64 => .NONE, .spir64 => .NONE, .wasm64 => .NONE, .amdgcn => .AMDGPU, @@ -1213,7 +1209,6 @@ pub const Cpu = struct { .xcore => .Unknown, .xtensa => .Unknown, .nvptx => .Unknown, - .hsail => .Unknown, .spir => .Unknown, .kalimba => .Unknown, .shave => .Unknown, @@ -1229,7 +1224,6 @@ pub const Cpu = struct { .riscv64 => .RISCV64, .x86_64 => .X64, .nvptx64 => .Unknown, - .hsail64 => .Unknown, .spir64 => .Unknown, .wasm64 => .Unknown, .amdgcn => .Unknown, @@ -1259,8 +1253,6 @@ pub const Cpu = struct { .csky, .xtensa, .hexagon, - .hsail, - .hsail64, .kalimba, .mipsel, .mips64el, @@ -1764,8 +1756,6 @@ pub const DynamicLinker = struct { .tce, .tcele, .xcore, - .hsail, - .hsail64, .spir, .spir64, .kalimba, @@ -1868,7 +1858,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .x86, .xcore, .nvptx, - .hsail, .spir, .kalimba, .shave, @@ -1890,7 +1879,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .riscv64, .x86_64, .nvptx64, - .hsail64, .spir64, .wasm64, .amdgcn, @@ -2390,7 +2378,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .hsail, .spir, .spirv32, .kalimba, @@ -2405,7 +2392,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .bpfel, .bpfeb, .hexagon, - .hsail64, .loongarch64, .m68k, .mips, @@ -2504,7 +2490,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .hsail, .spir, .spirv32, .kalimba, @@ -2525,7 +2510,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .bpfel, .bpfeb, .hexagon, - .hsail64, .x86, .loongarch64, .m68k, diff --git a/src/Type.zig b/src/Type.zig index 093bd2cbbe..411e242628 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1650,13 +1650,11 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .m68k, .tce, .tcele, - .hsail, .spir, .kalimba, .spirv, .spirv32, .shave, - .hsail64, .spir64, .ve, .spirv64, diff --git a/src/Zcu.zig b/src/Zcu.zig index b3b93507f4..8d1d2a5130 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment( .thumbeb, .x86, .xcore, - .hsail, .spir, .kalimba, .lanai, @@ -3279,7 +3278,6 @@ pub fn atomicPtrAlignment( .riscv64, .sparc64, .s390x, - .hsail64, .spir64, .wasm64, .ve, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index a4c417c6e6..90a5d4bf62 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .hsail => "hsail", - .hsail64 => "hsail64", .spir => "spir", .spir64 => "spir64", .spirv => "spirv", @@ -301,8 +299,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .xtensa => .xtensa, .nvptx => .nvptx, .nvptx64 => .nvptx64, - .hsail => .hsail, - .hsail64 => .hsail64, .spir => .spir, .spir64 => .spir64, .spirv => .spirv, @@ -12084,8 +12080,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { // LLVM backends that have no initialization functions. .tce, .tcele, - .hsail, - .hsail64, .shave, .spir, .spir64, diff --git a/src/target.zig b/src/target.zig index 3e213df4f6..dce8cab7b4 100644 --- a/src/target.zig +++ b/src/target.zig @@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .xtensa, .nvptx, .nvptx64, - .hsail, - .hsail64, .spir, .spir64, .spirv,