mirror of
https://github.com/ziglang/zig.git
synced 2026-01-20 14:25:16 +00:00
Cleaned up CPU detection and fixed incorrect detection bits.
This commit is contained in:
alichay
Andrew Kelley
parent
e24f29bbad
commit
f199182567
@ -171,6 +171,8 @@ pub const NativeTargetInfo = struct {
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dynamic_linker: DynamicLinker = DynamicLinker{},
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cpu_detected: bool = false,
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pub const DynamicLinker = Target.DynamicLinker;
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pub const DetectError = error{
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@ -191,6 +193,9 @@ pub const NativeTargetInfo = struct {
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/// deinitialization method.
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/// TODO Remove the Allocator requirement from this function.
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pub fn detect(allocator: *Allocator, cross_target: CrossTarget) DetectError!NativeTargetInfo {
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var cpu_detected = true;
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const cpu = switch (cross_target.cpu_model) {
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.native => detectNativeCpuAndFeatures(cross_target),
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.baseline => baselineCpuAndFeatures(cross_target),
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@ -203,6 +208,11 @@ pub const NativeTargetInfo = struct {
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cross_target.updateCpuFeatures(&adjusted_model.features);
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break :blk adjusted_model;
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},
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} orelse backup_cpu_detection: {
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// Temporarily use LLVM's cpu info as a backup
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cpu_detected = false;
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break :backup_cpu_detection baselineCpuAndFeatures(cross_target);
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};
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var os = Target.Os.defaultVersionRange(cross_target.getOsTag());
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@ -318,7 +328,9 @@ pub const NativeTargetInfo = struct {
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os.version_range.linux.glibc = glibc;
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}
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return detectAbiAndDynamicLinker(allocator, cpu, os, cross_target);
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var target = try detectAbiAndDynamicLinker(allocator, cpu, os, cross_target);
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target.cpu_detected = cpu_detected;
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return target;
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}
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/// First we attempt to use the executable's own binary. If it is dynamically
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@ -843,19 +855,15 @@ pub const NativeTargetInfo = struct {
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}
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}
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fn detectNativeCpuAndFeatures(cross_target: CrossTarget) Target.Cpu {
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var baseline = baselineCpuAndFeatures(cross_target);
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fn detectNativeCpuAndFeatures(cross_target: CrossTarget) ?Target.Cpu {
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switch(Target.current.cpu.arch) {
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.x86_64, .i386 => {
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const x86_detection = @import("system/x86.zig");
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x86_detection.detectNativeCpuAndFeatures(&baseline);
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return baseline;
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return @import("system/x86.zig").detectNativeCpuAndFeatures(cross_target);
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},
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else => {
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// // TODO Detect native CPU model & features. Until that is implemented we use baseline.
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return baseline;
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// TODO flesh out CPU detection for more than just x86.
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return null;
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}
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}
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}
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@ -10,70 +10,66 @@ fn setFeature(cpu: *Target.Cpu, feature: Target.x86.Feature, enabled: bool) void
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else cpu.features.removeFeature(idx);
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}
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fn hasFeature(cpu: *Target.Cpu, feature: Target.x86.Feature) bool {
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const idx = @as(Target.Cpu.Feature.Set.Index, @enumToInt(feature));
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return cpu.features.isEnabled(idx);
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}
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inline fn bit(input: u32, offset: u5) bool {
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return (input >> offset) & 1 != 0;
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}
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pub fn detectNativeCpuAndFeatures(cpu: *Target.Cpu) void {
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pub fn detectNativeCpuAndFeatures(cross_target: CrossTarget) Target.Cpu {
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defer {
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// Whenever we find a model, add that model's featureset.
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cpu.features.addFeatureSet(cpu.model.features);
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}
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var arch = cross_target.getCpuArch();
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// When we can't identify a specific model,
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// we guess based on processor features.
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// This seems to be the accepted standard.
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var cpu = Target.Cpu {
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.arch = arch,
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.model = Target.Cpu.Model.baseline(arch),
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.features = Target.Cpu.Feature.Set.empty,
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};
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detectNativeFeatures(cpu);
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detectNativeFeatures(&cpu, cross_target.getOsTag());
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var leaf = cpuid(0, 0);
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const max_leaf = leaf.eax;
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const vendor = leaf.ebx;
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if(max_leaf < 1) {
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cpu.model = &Target.x86.cpu.generic;
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return;
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}
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leaf = cpuid(0x1, 0);
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if(max_leaf > 0) {
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const brand_id = leaf.ebx & 0xff;
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var family: u32 = 0;
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var model: u32 = 0;
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leaf = cpuid(0x1, 0);
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{ // Detect model and family
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family = (leaf.eax >> 8) & 0xf;
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model = (leaf.eax >> 4) & 0xf;
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if (family == 6 or family == 0xf) {
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if (family == 0xf) {
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family += (leaf.eax >> 20) & 0xff;
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const brand_id = leaf.ebx & 0xff;
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var family: u32 = 0;
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var model: u32 = 0;
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{ // Detect model and family
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family = (leaf.eax >> 8) & 0xf;
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model = (leaf.eax >> 4) & 0xf;
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if (family == 6 or family == 0xf) {
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if (family == 0xf) {
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family += (leaf.eax >> 20) & 0xff;
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}
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model += ((leaf.eax >> 16) & 0xf) << 4;
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}
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model += ((leaf.eax >> 16) & 0xf) << 4;
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}
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switch(vendor) {
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0x756e6547 => {
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detectIntelProcessor(&cpu, family, model, brand_id);
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},
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0x68747541 => {
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detectAMDProcessor(&cpu, family, model);
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},
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else => {},
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}
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}
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switch(vendor) {
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0x756e6547 => {
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detectIntelProcessor(cpu, family, model, brand_id);
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},
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0x68747541 => {
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detectAMDProcessor(cpu, family, model);
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},
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else => {
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cpu.model = &Target.x86.cpu.generic;
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},
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}
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var model_features = cpu.model.features;
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model_features.populateDependencies(cpu.arch.allFeaturesList());
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cpu.features.addFeatureSet(model_features);
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return cpu;
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}
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fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32) void {
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if (brand_id != 0) {
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cpu.model = &Target.x86.cpu.generic;
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return;
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}
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switch(family) {
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@ -86,7 +82,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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5 => {
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if(hasFeature(cpu, .mmx)) {
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if(Target.x86.featureSetHas(cpu.features, .mmx)) {
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cpu.model = &Target.x86.cpu.pentium_mmx;
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return;
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}
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@ -152,10 +148,10 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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0x55 => {
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if(hasFeature(cpu, .avx512bf16)) {
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if(Target.x86.featureSetHas(cpu.features, .avx512bf16)) {
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cpu.model = &Target.x86.cpu.cooperlake;
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return;
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} else if(hasFeature(cpu, .avx512vnni)) {
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} else if(Target.x86.featureSetHas(cpu.features, .avx512vnni)) {
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cpu.model = &Target.x86.cpu.cascadelake;
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return;
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} else {
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@ -204,114 +200,18 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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else => {
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// Unknown, try to guess.
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// TODO detect tigerlake host
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if(hasFeature(cpu, .avx512vp2intersect)) {
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// TODO no tigerlake entry in Target.x86.cpu
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//cpu.model = &Target.x86.cpu.tigerlake;
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cpu.model = &Target.x86.cpu.nehalem;
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return;
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}
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if(hasFeature(cpu, .avx512vbmi2)) {
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cpu.model = &Target.x86.cpu.icelake_client;
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return;
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}
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if(hasFeature(cpu, .avx512vbmi)) {
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cpu.model = &Target.x86.cpu.cannonlake;
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return;
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}
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if(hasFeature(cpu, .avx512bf16)) {
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cpu.model = &Target.x86.cpu.cooperlake;
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return;
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}
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if(hasFeature(cpu, .avx512vnni)) {
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cpu.model = &Target.x86.cpu.cascadelake;
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return;
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}
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if(hasFeature(cpu, .avx512vl)) {
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cpu.model = &Target.x86.cpu.skylake_avx512;
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return;
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}
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if(hasFeature(cpu, .avx512er)) {
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cpu.model = &Target.x86.cpu.knl;
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return;
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}
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if(hasFeature(cpu, .clflushopt)) {
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if(hasFeature(cpu, .sha)) {
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cpu.model = &Target.x86.cpu.goldmont;
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return;
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} else {
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cpu.model = &Target.x86.cpu.skylake;
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return;
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}
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}
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if(hasFeature(cpu, .adx)) {
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cpu.model = &Target.x86.cpu.broadwell;
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return;
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}
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if(hasFeature(cpu, .avx2)) {
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cpu.model = &Target.x86.cpu.haswell;
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return;
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}
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if(hasFeature(cpu, .avx)) {
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cpu.model = &Target.x86.cpu.sandybridge;
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return;
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}
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if(hasFeature(cpu, .sse4_2)) {
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if(hasFeature(cpu, .movbe)) {
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cpu.model = &Target.x86.cpu.silvermont;
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return;
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} else {
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cpu.model = &Target.x86.cpu.nehalem;
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return;
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}
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}
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if(hasFeature(cpu, .sse4_1)) {
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cpu.model = &Target.x86.cpu.penryn;
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return;
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}
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if(hasFeature(cpu, .sse3)) {
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if(hasFeature(cpu, .movbe)) {
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cpu.model = &Target.x86.cpu.bonnell;
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return;
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} else {
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cpu.model = &Target.x86.cpu.core2;
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return;
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}
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}
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if(hasFeature(cpu, .@"64bit")) {
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cpu.model = &Target.x86.cpu.core2;
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return;
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}
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if(hasFeature(cpu, .sse3)) {
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cpu.model = &Target.x86.cpu.yonah;
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return;
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}
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if(hasFeature(cpu, .sse2)) {
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cpu.model = &Target.x86.cpu.pentium_m;
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return;
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}
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if(hasFeature(cpu, .sse)) {
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cpu.model = &Target.x86.cpu.pentium3;
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return;
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}
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if(hasFeature(cpu, .mmx)) {
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cpu.model = &Target.x86.cpu.pentium2;
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return;
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}
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cpu.model = &Target.x86.cpu.pentiumpro;
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// Unknown CPU.
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// Default to baseline x86_64 or i386 cpu.
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return;
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},
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}
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},
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15 => {
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if(hasFeature(cpu, .@"64bit")) {
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if(Target.x86.featureSetHas(cpu.features, .@"64bit")) {
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cpu.model = &Target.x86.cpu.nocona;
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return;
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}
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if(hasFeature(cpu, .sse3)) {
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if(Target.x86.featureSetHas(cpu.features, .sse3)) {
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cpu.model = &Target.x86.cpu.prescott;
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return;
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}
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@ -319,7 +219,8 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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else => {
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cpu.model = &Target.x86.cpu.generic;
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// Unknown CPU.
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// Default to baseline x86_64 or i386 cpu.
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return;
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}
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}
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@ -358,7 +259,7 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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return;
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},
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6 => {
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if(hasFeature(cpu, .sse)) {
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if(Target.x86.featureSetHas(cpu.features, .sse)) {
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cpu.model = &Target.x86.cpu.athlon_xp;
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return;
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}
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@ -366,7 +267,7 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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return;
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},
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15 => {
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if(hasFeature(cpu, .sse3)) {
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if(Target.x86.featureSetHas(cpu.features, .sse3)) {
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cpu.model = &Target.x86.cpu.k8_sse3;
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return;
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}
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@ -410,13 +311,12 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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return;
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},
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else => {
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cpu.model = &Target.x86.cpu.generic;
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return;
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}
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}
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}
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fn detectNativeFeatures(cpu: *Target.Cpu) void {
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fn detectNativeFeatures(cpu: *Target.Cpu, os_type: Target.Os.Tag) void {
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var leaf = cpuid(0, 0);
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@ -442,23 +342,42 @@ fn detectNativeFeatures(cpu: *Target.Cpu) void {
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setFeature(cpu, .aes, bit(leaf.ecx, 25));
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setFeature(cpu, .rdrnd, bit(leaf.ecx, 30));
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const has_avx_save = bit(leaf.ecx, 27) and
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bit(leaf.ecx, 28) and
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((leaf.eax & 0x6) == 0x6);
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leaf.eax = getXCR0();
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const has_avx = bit(leaf.ecx, 27) and
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bit(leaf.ecx, 28) and
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((leaf.eax & 0x6) == 0x6);
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// LLVM approaches avx512_save by hardcoding it to true on Darwin,
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// because the kernel saves the context even if the bit is not set.
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// https://github.com/llvm/llvm-project/blob/bca373f73fc82728a8335e7d6cd164e8747139ec/llvm/lib/Support/Host.cpp#L1378
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//
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// Google approaches this by using a different series of checks and flags,
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// and this may report the feature more accurately on a technically correct
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// but ultimately less useful level.
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// https://github.com/google/cpu_features/blob/b5c271c53759b2b15ff91df19bd0b32f2966e275/src/cpuinfo_x86.c#L113
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// (called from https://github.com/google/cpu_features/blob/b5c271c53759b2b15ff91df19bd0b32f2966e275/src/cpuinfo_x86.c#L1052)
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//
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// Right now, we use LLVM's approach, because even if the target doesn't support
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// the feature, the kernel should provide the same functionality transparently,
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// so the implementation details don't make a difference.
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// That said, this flag impacts other CPU features' availability,
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// so until we can verify that this doesn't come with side affects,
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// we'll say TODO verify this.
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// Darwin lazily saves the AVX512 context on first use: trust that the OS will
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// save the AVX512 context if we use AVX512 instructions, even the bit is not
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// save the AVX512 context if we use AVX512 instructions, even if the bit is not
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// set right now.
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const has_avx512_save = switch(Target.current.isDarwin()) {
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const has_avx512_save = switch(os_type.isDarwin()) {
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true => true,
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false => has_avx_save and ((leaf.eax & 0xE0) == 0xE0),
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false => has_avx and ((leaf.eax & 0xE0) == 0xE0),
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};
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setFeature(cpu, .avx, has_avx_save);
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setFeature(cpu, .fma, has_avx_save and bit(leaf.ecx, 12));
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setFeature(cpu, .avx, has_avx);
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setFeature(cpu, .fma, has_avx and bit(leaf.ecx, 12));
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// Only enable XSAVE if OS has enabled support for saving YMM state.
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setFeature(cpu, .xsave, has_avx_save and bit(leaf.ecx, 26));
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setFeature(cpu, .f16c, has_avx_save and bit(leaf.ecx, 29));
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setFeature(cpu, .xsave, has_avx and bit(leaf.ecx, 26));
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setFeature(cpu, .f16c, has_avx and bit(leaf.ecx, 29));
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leaf = cpuid(0x80000000, 0);
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const max_ext_level = leaf.eax;
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@ -469,9 +388,9 @@ fn detectNativeFeatures(cpu: *Target.Cpu) void {
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setFeature(cpu, .lzcnt, bit(leaf.ecx, 5));
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setFeature(cpu, .sse4a, bit(leaf.ecx, 6));
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setFeature(cpu, .prfchw, bit(leaf.ecx, 8));
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setFeature(cpu, .xop, bit(leaf.ecx, 11) and has_avx_save);
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setFeature(cpu, .xop, bit(leaf.ecx, 11) and has_avx);
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setFeature(cpu, .lwp, bit(leaf.ecx, 15));
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setFeature(cpu, .fma4, bit(leaf.ecx, 16) and has_avx_save);
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setFeature(cpu, .fma4, bit(leaf.ecx, 16) and has_avx);
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setFeature(cpu, .tbm, bit(leaf.ecx, 21));
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setFeature(cpu, .mwaitx, bit(leaf.ecx, 29));
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setFeature(cpu, .@"64bit", bit(leaf.edx, 29));
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@ -486,7 +405,7 @@ fn detectNativeFeatures(cpu: *Target.Cpu) void {
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// Misc. memory-related features.
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if(max_ext_level >= 0x80000008) {
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leaf = cpuid(80000008, 0);
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leaf = cpuid(0x80000008, 0);
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setFeature(cpu, .clzero, bit(leaf.ebx, 0));
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setFeature(cpu, .wbnoinvd, bit(leaf.ebx, 9));
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} else {
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@ -495,14 +414,14 @@ fn detectNativeFeatures(cpu: *Target.Cpu) void {
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}
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}
|
||||
|
||||
if(max_level >= 7) {
|
||||
if(max_level >= 0x7) {
|
||||
leaf = cpuid(0x7, 0);
|
||||
|
||||
setFeature(cpu, .fsgsbase, bit(leaf.ebx, 0));
|
||||
setFeature(cpu, .sgx, bit(leaf.ebx, 2));
|
||||
setFeature(cpu, .bmi, bit(leaf.ebx, 3));
|
||||
// AVX2 is only supported if we have the OS save support from AVX.
|
||||
setFeature(cpu, .avx2, bit(leaf.ebx, 5) and has_avx_save);
|
||||
setFeature(cpu, .avx2, bit(leaf.ebx, 5) and has_avx);
|
||||
setFeature(cpu, .bmi2, bit(leaf.ebx, 8));
|
||||
setFeature(cpu, .invpcid, bit(leaf.ebx, 10));
|
||||
setFeature(cpu, .rtm, bit(leaf.ebx, 11));
|
||||
@ -528,8 +447,8 @@ fn detectNativeFeatures(cpu: *Target.Cpu) void {
|
||||
setFeature(cpu, .avx512vbmi2, bit(leaf.ecx, 6) and has_avx512_save);
|
||||
setFeature(cpu, .shstk, bit(leaf.ecx, 7));
|
||||
setFeature(cpu, .gfni, bit(leaf.ecx, 8));
|
||||
setFeature(cpu, .vaes, bit(leaf.ecx, 9) and has_avx_save);
|
||||
setFeature(cpu, .vpclmulqdq, bit(leaf.ecx, 10) and has_avx_save);
|
||||
setFeature(cpu, .vaes, bit(leaf.ecx, 9) and has_avx);
|
||||
setFeature(cpu, .vpclmulqdq, bit(leaf.ecx, 10) and has_avx);
|
||||
setFeature(cpu, .avx512vnni, bit(leaf.ecx, 11) and has_avx512_save);
|
||||
setFeature(cpu, .avx512bitalg, bit(leaf.ecx, 12) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vpopcntdq, bit(leaf.ecx, 14) and has_avx512_save);
|
||||
@ -580,7 +499,7 @@ fn detectNativeFeatures(cpu: *Target.Cpu) void {
|
||||
}
|
||||
}
|
||||
|
||||
if(max_level >= 0xD and has_avx_save) {
|
||||
if(max_level >= 0xD and has_avx) {
|
||||
leaf = cpuid(0xD, 0x1);
|
||||
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
||||
setFeature(cpu, .xsaveopt, bit(leaf.eax, 0));
|
||||
|
||||
@ -1154,8 +1154,7 @@ fn enumInt(comptime Enum: type, int: c_int) Enum {
|
||||
|
||||
fn crossTargetToTarget(cross_target: CrossTarget, dynamic_linker_ptr: *?[*:0]u8) !Target {
|
||||
var info = try std.zig.system.NativeTargetInfo.detect(std.heap.c_allocator, cross_target);
|
||||
if ((cross_target.cpu_arch == null or cross_target.cpu_model == .native) and
|
||||
(Target.current.cpu.arch != .i386 and Target.current.cpu.arch != .x86_64)) {
|
||||
if ((cross_target.cpu_arch == null or cross_target.cpu_model == .native) and !info.cpu_detected) {
|
||||
// TODO We want to just use detected_info.target but implementing
|
||||
// CPU model & feature detection is todo so here we rely on LLVM.
|
||||
const llvm = @import("llvm.zig");
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user