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https://github.com/ziglang/zig.git
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x64: migrate div to genMulDivBinOp
This commit is contained in:
Jakub Konka
parent
85ca14e35a
commit
ef9e3fb2b6
@ -592,11 +592,11 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.sub => try self.airBinOp(inst),
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.subwrap => try self.airBinOp(inst),
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.sub_sat => try self.airSubSat(inst),
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.mul => try self.airBinOp(inst),
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.mulwrap => try self.airBinOp(inst),
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.mul => try self.airMulDivBinOp(inst),
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.mulwrap => try self.airMulDivBinOp(inst),
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.mul_sat => try self.airMulSat(inst),
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.rem => try self.airBinOp(inst),
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.mod => try self.airBinOp(inst),
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.rem => try self.airMulDivBinOp(inst),
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.mod => try self.airMulDivBinOp(inst),
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.shl, .shl_exact => try self.airShl(inst),
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.shl_sat => try self.airShlSat(inst),
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.min => try self.airMin(inst),
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@ -626,7 +626,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.mul_with_overflow => try self.airMulWithOverflow(inst),
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.shl_with_overflow => try self.airShlWithOverflow(inst),
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.div_float, .div_trunc, .div_floor, .div_exact => try self.airDiv(inst),
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.div_float, .div_trunc, .div_floor, .div_exact => try self.airMulDivBinOp(inst),
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.cmp_lt => try self.airCmp(inst, .lt),
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.cmp_lte => try self.airCmp(inst, .lte),
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@ -959,6 +959,12 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
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}
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}
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pub fn spillRegisters(self: *Self, comptime count: comptime_int, registers: [count]Register) !void {
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for (registers) |reg| {
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try self.register_manager.getReg(reg, null);
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}
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}
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/// Copies a value to a register without tracking the register. The register is not considered
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/// allocated. A second call to `copyToTmpRegister` may return the same register.
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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@ -1252,6 +1258,26 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst)) {
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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const tag = self.air.instructions.items(.tag)[inst];
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const ty = self.air.typeOfIndex(inst);
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try self.spillRegisters(2, .{ .rax, .rdx });
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const result = try self.genMulDivBinOp(tag, inst, ty, lhs, rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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@ -1339,25 +1365,31 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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return self.fail("TODO implement mul_with_overflow for Ints larger than 64bits", .{});
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}
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try self.spillCompareFlagsIfOccupied();
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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if (math.isPowerOfTwo(int_info.bits)) {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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const partial = try self.genBinOp(.mul, null, lhs, rhs, ty, ty);
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try self.spillRegisters(2, .{ .rax, .rdx });
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const partial = try self.genMulDivBinOp(.mul, null, ty, lhs, rhs);
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break :result switch (int_info.signedness) {
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.signed => MCValue{ .register_overflow_signed = partial.register },
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.unsigned => MCValue{ .register_overflow_unsigned = partial.register },
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};
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}
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = null;
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const dst_reg: Register = dst_reg: {
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switch (int_info.signedness) {
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.signed => {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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@ -1386,7 +1418,12 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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break :dst_reg dst_reg;
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},
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.unsigned => {
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const dst_mcv = try self.genBinOp(.mul, null, lhs, rhs, ty, ty);
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try self.spillRegisters(2, .{ .rax, .rdx });
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const dst_mcv = try self.genMulDivBinOp(.mul, null, ty, lhs, rhs);
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break :dst_reg dst_mcv.register;
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},
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}
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@ -1487,7 +1524,13 @@ fn genIntMulDivOpMir(
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return self.fail("TODO implement genIntMulDivOpMir for ABI size larger than 8", .{});
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}
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try self.genSetReg(ty, .rax, lhs);
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lhs: {
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switch (lhs) {
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.register => |reg| if (reg.to64() == .rax) break :lhs,
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else => {},
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}
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try self.genSetReg(ty, .rax, lhs);
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}
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switch (signedness) {
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.signed => {
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@ -1609,96 +1652,6 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
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return MCValue{ .register = divisor };
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}
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fn airDiv(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst)) {
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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const tag = self.air.instructions.items(.tag)[inst];
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const ty = self.air.typeOfIndex(inst);
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if (ty.zigTypeTag() != .Int) {
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return self.fail("TODO implement {} for operands of dst type {}", .{ tag, ty.zigTypeTag() });
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}
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if (tag == .div_float) {
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return self.fail("TODO implement {}", .{tag});
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}
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const signedness = ty.intInfo(self.target.*).signedness;
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// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
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const track_rax: ?Air.Inst.Index = blk: {
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if (signedness == .unsigned) break :blk inst;
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switch (tag) {
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.div_exact, .div_trunc => break :blk inst,
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else => break :blk null,
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}
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};
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try self.register_manager.getReg(.rax, track_rax);
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try self.register_manager.getReg(.rdx, null);
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const reg_locks = self.register_manager.lockRegsAssumeUnused(2, .{ .rax, .rdx });
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defer for (reg_locks) |reg| {
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self.register_manager.unlockReg(reg);
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};
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const lhs = try self.resolveInst(bin_op.lhs);
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs: MCValue = blk: {
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const rhs = try self.resolveInst(bin_op.rhs);
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if (signedness == .signed) {
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switch (tag) {
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.div_floor => {
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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break :blk try self.copyToRegisterWithInstTracking(inst, ty, rhs);
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},
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else => {},
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}
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}
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break :blk rhs;
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};
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const result: MCValue = result: {
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if (signedness == .unsigned) {
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try self.genIntMulDivOpMir(.div, ty, signedness, lhs, rhs);
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break :result MCValue{ .register = .rax };
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}
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switch (tag) {
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.div_exact, .div_trunc => {
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try self.genIntMulDivOpMir(switch (signedness) {
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.signed => .idiv,
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.unsigned => .div,
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}, ty, signedness, lhs, rhs);
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break :result MCValue{ .register = .rax };
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},
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.div_floor => {
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break :result try self.genInlineIntDivFloor(ty, lhs, rhs);
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},
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else => unreachable,
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airShl(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst)) {
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@ -3143,6 +3096,170 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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/// Result is always a register.
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/// Clobbers .rax and .rdx therefore care needs to be taken to spill operands upfront.
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/// Asserts .rax and .rdx are free.
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fn genMulDivBinOp(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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ty: Type,
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lhs: MCValue,
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rhs: MCValue,
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) !MCValue {
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if (ty.zigTypeTag() == .Vector or ty.zigTypeTag() == .Float) {
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return self.fail("TODO implement genBinOp for {}", .{ty.fmtDebug()});
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}
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if (ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genBinOp for {}", .{ty.fmtDebug()});
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}
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if (tag == .div_float) {
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return self.fail("TODO implement genMulDivBinOp for div_float", .{});
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}
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assert(self.register_manager.isRegFree(.rax));
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assert(self.register_manager.isRegFree(.rdx));
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const reg_locks = self.register_manager.lockRegsAssumeUnused(2, .{ .rax, .rdx });
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defer for (reg_locks) |reg| {
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self.register_manager.unlockReg(reg);
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};
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const int_info = ty.intInfo(self.target.*);
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const signedness = int_info.signedness;
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switch (tag) {
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.mul,
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.mulwrap,
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=> {
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try self.register_manager.getReg(.rax, maybe_inst);
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try self.register_manager.getReg(.rdx, null);
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try self.genIntMulDivOpMir(switch (signedness) {
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.signed => .imul,
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.unsigned => .mul,
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}, ty, signedness, lhs, rhs);
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return switch (signedness) {
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.signed => MCValue{ .register = .rax },
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.unsigned => MCValue{ .register = registerAlias(.rax, @intCast(u32, ty.abiSize(self.target.*))) },
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};
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},
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.mod,
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.rem,
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=> {
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const track_inst_rdx: ?Air.Inst.Index = switch (tag) {
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.mod => if (signedness == .unsigned) maybe_inst else null,
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.rem => maybe_inst,
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else => unreachable,
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};
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rdx, track_inst_rdx);
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switch (signedness) {
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.signed => {
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switch (tag) {
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.rem => {
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try self.genIntMulDivOpMir(.idiv, ty, .signed, lhs, rhs);
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return MCValue{ .register = .rdx };
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},
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.mod => {
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const div_floor = try self.genInlineIntDivFloor(ty, lhs, rhs);
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try self.genIntMulComplexOpMir(ty, div_floor, rhs);
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const div_floor_lock = self.register_manager.lockReg(div_floor.register);
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defer if (div_floor_lock) |lock| self.register_manager.unlockReg(lock);
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const result: MCValue = if (maybe_inst) |inst|
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try self.copyToRegisterWithInstTracking(inst, ty, lhs)
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else
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MCValue{ .register = try self.copyToTmpRegister(ty, lhs) };
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try self.genBinOpMir(.sub, ty, result, div_floor);
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return result;
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},
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else => unreachable,
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}
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},
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.unsigned => {
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try self.genIntMulDivOpMir(.div, ty, .unsigned, lhs, rhs);
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return MCValue{ .register = .rdx };
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},
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}
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},
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.div_trunc,
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.div_floor,
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.div_exact,
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=> {
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const track_inst_rax: ?Air.Inst.Index = blk: {
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if (signedness == .unsigned) break :blk maybe_inst;
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switch (tag) {
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.div_exact, .div_trunc => break :blk maybe_inst,
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else => break :blk null,
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}
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};
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try self.register_manager.getReg(.rax, track_inst_rax);
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try self.register_manager.getReg(.rdx, null);
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const actual_rhs: MCValue = blk: {
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if (signedness == .signed) {
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switch (tag) {
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.div_floor => {
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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if (maybe_inst) |inst| {
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break :blk try self.copyToRegisterWithInstTracking(inst, ty, rhs);
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}
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break :blk MCValue{ .register = try self.copyToTmpRegister(ty, rhs) };
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},
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else => {},
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}
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}
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break :blk rhs;
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};
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const rhs_lock: ?RegisterLock = switch (actual_rhs) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const result: MCValue = result: {
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if (signedness == .unsigned) {
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try self.genIntMulDivOpMir(.div, ty, signedness, lhs, actual_rhs);
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break :result MCValue{ .register = .rax };
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}
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switch (tag) {
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.div_exact, .div_trunc => {
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try self.genIntMulDivOpMir(switch (signedness) {
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.signed => .idiv,
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.unsigned => .div,
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}, ty, signedness, lhs, actual_rhs);
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break :result MCValue{ .register = .rax };
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},
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.div_floor => {
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break :result try self.genInlineIntDivFloor(ty, lhs, actual_rhs);
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},
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else => unreachable,
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}
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};
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return result;
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},
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else => unreachable,
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}
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}
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/// Result is always a register.
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fn genBinOp(
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self: *Self,
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@ -3153,6 +3270,13 @@ fn genBinOp(
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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if (lhs_ty.zigTypeTag() == .Vector or lhs_ty.zigTypeTag() == .Float) {
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return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
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}
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if (lhs_ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
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}
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const is_commutative: bool = switch (tag) {
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.add,
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.addwrap,
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@ -3163,106 +3287,9 @@ fn genBinOp(
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.xor,
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=> true,
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.sub,
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.subwrap,
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.mul,
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.mulwrap,
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.div_exact,
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.div_trunc,
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.rem,
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.mod,
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.shl,
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.shr,
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.ptr_add,
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.ptr_sub,
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=> false,
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.div_float => return self.fail("TODO implement genBinOp for {}", .{tag}),
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else => unreachable,
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else => false,
|
||||
};
|
||||
|
||||
if (lhs_ty.zigTypeTag() == .Vector or lhs_ty.zigTypeTag() == .Float) {
|
||||
return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
|
||||
}
|
||||
if (lhs_ty.abiSize(self.target.*) > 8) {
|
||||
return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
|
||||
}
|
||||
|
||||
switch (tag) {
|
||||
.mul,
|
||||
.mulwrap,
|
||||
=> {
|
||||
// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
|
||||
try self.register_manager.getReg(.rax, maybe_inst);
|
||||
try self.register_manager.getReg(.rdx, null);
|
||||
const reg_locks = self.register_manager.lockRegsAssumeUnused(2, .{ .rax, .rdx });
|
||||
defer for (reg_locks) |reg| {
|
||||
self.register_manager.unlockReg(reg);
|
||||
};
|
||||
|
||||
const int_info = lhs_ty.intInfo(self.target.*);
|
||||
try self.genIntMulDivOpMir(switch (int_info.signedness) {
|
||||
.signed => .imul,
|
||||
.unsigned => .mul,
|
||||
}, lhs_ty, int_info.signedness, lhs, rhs);
|
||||
|
||||
return switch (int_info.signedness) {
|
||||
.signed => MCValue{ .register = .rax },
|
||||
.unsigned => MCValue{ .register = registerAlias(.rax, @intCast(u32, lhs_ty.abiSize(self.target.*))) },
|
||||
};
|
||||
},
|
||||
.mod,
|
||||
.rem,
|
||||
=> {
|
||||
const int_info = lhs_ty.intInfo(self.target.*);
|
||||
const track_inst_rdx: ?Air.Inst.Index = switch (tag) {
|
||||
.mod => if (int_info.signedness == .unsigned) maybe_inst else null,
|
||||
.rem => maybe_inst,
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
|
||||
try self.register_manager.getReg(.rax, null);
|
||||
try self.register_manager.getReg(.rdx, track_inst_rdx);
|
||||
const reg_locks = self.register_manager.lockRegsAssumeUnused(2, .{ .rax, .rdx });
|
||||
defer for (reg_locks) |reg| {
|
||||
self.register_manager.unlockReg(reg);
|
||||
};
|
||||
|
||||
switch (int_info.signedness) {
|
||||
.signed => {
|
||||
switch (tag) {
|
||||
.rem => {
|
||||
try self.genIntMulDivOpMir(.idiv, lhs_ty, .signed, lhs, rhs);
|
||||
return MCValue{ .register = .rdx };
|
||||
},
|
||||
.mod => {
|
||||
const div_floor = try self.genInlineIntDivFloor(lhs_ty, lhs, rhs);
|
||||
try self.genIntMulComplexOpMir(lhs_ty, div_floor, rhs);
|
||||
const div_floor_lock = self.register_manager.lockReg(div_floor.register);
|
||||
defer if (div_floor_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
|
||||
const result: MCValue = if (maybe_inst) |inst|
|
||||
try self.copyToRegisterWithInstTracking(inst, lhs_ty, lhs)
|
||||
else
|
||||
MCValue{ .register = try self.copyToTmpRegister(lhs_ty, lhs) };
|
||||
try self.genBinOpMir(.sub, lhs_ty, result, div_floor);
|
||||
|
||||
return result;
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
},
|
||||
.unsigned => {
|
||||
try self.genIntMulDivOpMir(.div, lhs_ty, .unsigned, lhs, rhs);
|
||||
return MCValue{ .register = .rdx };
|
||||
},
|
||||
}
|
||||
},
|
||||
else => {},
|
||||
}
|
||||
|
||||
const lhs_lock: ?RegisterLock = switch (lhs) {
|
||||
.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
|
||||
else => null,
|
||||
@ -5460,6 +5487,7 @@ fn genInlineMemcpy(
|
||||
len: MCValue,
|
||||
opts: InlineMemcpyOpts,
|
||||
) InnerError!void {
|
||||
// TODO preserve contents of .rax and .rcx if not free, and then restore
|
||||
try self.register_manager.getReg(.rax, null);
|
||||
try self.register_manager.getReg(.rcx, null);
|
||||
|
||||
@ -5657,6 +5685,7 @@ fn genInlineMemset(
|
||||
len: MCValue,
|
||||
opts: InlineMemcpyOpts,
|
||||
) InnerError!void {
|
||||
// TODO preserve contents of .rax and then restore
|
||||
try self.register_manager.getReg(.rax, null);
|
||||
const rax_lock = self.register_manager.lockRegAssumeUnused(.rax);
|
||||
defer self.register_manager.unlockReg(rax_lock);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user