diff --git a/lib/std/Target/spirv.zig b/lib/std/Target/spirv.zig index ca83ad2d26..a2575b2fe8 100644 --- a/lib/std/Target/spirv.zig +++ b/lib/std/Target/spirv.zig @@ -10,8 +10,6 @@ pub const Feature = enum { v1_4, v1_5, v1_6, - int8, - int16, int64, float16, float64, @@ -71,16 +69,6 @@ pub const all_features = blk: { .description = "Enable version 1.6", .dependencies = featureSet(&[_]Feature{.v1_5}), }; - result[@intFromEnum(Feature.int8)] = .{ - .llvm_name = null, - .description = "Enable Int8 capability", - .dependencies = featureSet(&[_]Feature{.v1_0}), - }; - result[@intFromEnum(Feature.int16)] = .{ - .llvm_name = null, - .description = "Enable Int16 capability", - .dependencies = featureSet(&[_]Feature{.v1_0}), - }; result[@intFromEnum(Feature.int64)] = .{ .llvm_name = null, .description = "Enable Int64 capability", @@ -109,7 +97,7 @@ pub const all_features = blk: { result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{ .llvm_name = null, .description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability", - .dependencies = featureSet(&[_]Feature{ .v1_5, .int8, .int16 }), + .dependencies = featureSet(&[_]Feature{.v1_5}), }; result[@intFromEnum(Feature.kernel)] = .{ .llvm_name = null, diff --git a/src/codegen/spirv.zig b/src/codegen/spirv.zig index 899a8db7fe..c361090b51 100644 --- a/src/codegen/spirv.zig +++ b/src/codegen/spirv.zig @@ -588,11 +588,11 @@ const NavGen = struct { if (self.spv.hasFeature(.arbitrary_precision_integers) and bits <= 32) return bits; - // 8, 16 and 64-bit integers require the Int8, Int16 and Inr64 capabilities respectively. + // We require Int8 and Int16 capabilities and benefit Int64 when available. // 32-bit integers are always supported (see spec, 2.16.1, Data rules). const ints = [_]struct { bits: u16, feature: ?Target.spirv.Feature }{ - .{ .bits = 8, .feature = .int8 }, - .{ .bits = 16, .feature = .int16 }, + .{ .bits = 8, .feature = null }, + .{ .bits = 16, .feature = null }, .{ .bits = 32, .feature = null }, .{ .bits = 64, .feature = .int64 }, }; @@ -1373,7 +1373,7 @@ const NavGen = struct { var member_types: [4]IdRef = undefined; var member_names: [4][]const u8 = undefined; - const u8_ty_id = try self.resolveType(Type.u8, .direct); // TODO: What if Int8Type is not enabled? + const u8_ty_id = try self.resolveType(Type.u8, .direct); if (layout.tag_size != 0) { const tag_ty_id = try self.resolveType(Type.fromInterned(union_obj.enum_tag_ty), .indirect); diff --git a/src/codegen/spirv/Module.zig b/src/codegen/spirv/Module.zig index 1acdc0915c..1aa082f6bc 100644 --- a/src/codegen/spirv/Module.zig +++ b/src/codegen/spirv/Module.zig @@ -333,8 +333,6 @@ pub fn finalize(self: *Module, a: Allocator) ![]Word { // Versions .v1_0, .v1_1, .v1_2, .v1_3, .v1_4, .v1_5, .v1_6 => {}, // Features with no dependencies - .int8 => try self.addCapability(.Int8), - .int16 => try self.addCapability(.Int16), .int64 => try self.addCapability(.Int64), .float16 => try self.addCapability(.Float16), .float64 => try self.addCapability(.Float64), @@ -361,6 +359,9 @@ pub fn finalize(self: *Module, a: Allocator) ![]Word { } } } + // These are well supported + try self.addCapability(.Int8); + try self.addCapability(.Int16); // Emit memory model const addressing_model: spec.AddressingModel = blk: { diff --git a/test/tests.zig b/test/tests.zig index 28c6fbc67e..9224f97c7e 100644 --- a/test/tests.zig +++ b/test/tests.zig @@ -143,7 +143,7 @@ const test_targets = blk: { .{ .target = std.Target.Query.parse(.{ .arch_os_abi = "spirv64-vulkan", - .cpu_features = "vulkan_v1_2+int8+int16+int64+float16+float64", + .cpu_features = "vulkan_v1_2+int64+float16+float64", }) catch unreachable, .use_llvm = false, .use_lld = false,