lol that's never going to happen in stage1

This commit is contained in:
Andrew Kelley 2021-05-27 17:39:18 -07:00
parent 2a990d6966
commit eb37722d79

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@ -2720,8 +2720,7 @@ enum IrInstGenId {
IrInstGenIdExtern,
};
// Common fields between IrInstSrc and IrInstGen. This allows future passes
// after pass2 to be added to zig.
// Common fields between IrInstSrc and IrInstGen.
struct IrInst {
// if ref_count is zero and the instruction has no side effects,
// the instruction can be omitted in codegen