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x86_64: implement @sqrt for f16 scalars and vectors
This commit is contained in:
Jacob Young
parent
5c5da179fb
commit
ea957c4cff
@ -4531,59 +4531,117 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
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const dst_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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const tag = if (@as(?Mir.Inst.Tag, switch (ty.zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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32 => if (self.hasFeature(.avx)) .vsqrtss else .sqrtss,
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64 => if (self.hasFeature(.avx)) .vsqrtsd else .sqrtsd,
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16, 80, 128 => null,
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else => unreachable,
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},
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.Vector => switch (ty.childType().zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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32 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vsqrtss else .sqrtss,
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2...4 => if (self.hasFeature(.avx)) .vsqrtps else .sqrtps,
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5...8 => if (self.hasFeature(.avx)) .vsqrtps else null,
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else => null,
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const result: MCValue = result: {
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const tag = if (@as(?Mir.Inst.Tag, switch (ty.zigTypeTag()) {
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.Float => switch (ty.floatBits(self.target.*)) {
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16 => if (self.hasFeature(.f16c)) {
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const mat_src_reg = if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, src_mcv);
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try self.asmRegisterRegister(.vcvtph2ps, dst_reg, mat_src_reg.to128());
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try self.asmRegisterRegisterRegister(.vsqrtss, dst_reg, dst_reg, dst_reg);
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try self.asmRegisterRegisterImmediate(
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.vcvtps2ph,
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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break :result dst_mcv;
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} else null,
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32 => if (self.hasFeature(.avx)) .vsqrtss else .sqrtss,
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64 => if (self.hasFeature(.avx)) .vsqrtsd else .sqrtsd,
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80, 128 => null,
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else => unreachable,
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},
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.Vector => switch (ty.childType().zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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16 => if (self.hasFeature(.f16c)) switch (ty.vectorLen()) {
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1 => {
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const mat_src_reg = if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, src_mcv);
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try self.asmRegisterRegister(.vcvtph2ps, dst_reg, mat_src_reg.to128());
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try self.asmRegisterRegisterRegister(.vsqrtss, dst_reg, dst_reg, dst_reg);
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try self.asmRegisterRegisterImmediate(
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.vcvtps2ph,
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dst_reg,
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dst_reg,
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Immediate.u(0b1_00),
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);
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break :result dst_mcv;
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},
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2...8 => {
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const wide_reg = registerAlias(dst_reg, abi_size * 2);
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if (src_mcv.isRegister()) try self.asmRegisterRegister(
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.vcvtph2ps,
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wide_reg,
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src_mcv.getReg().?.to128(),
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) else try self.asmRegisterMemory(
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.vcvtph2ps,
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wide_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(
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@intCast(u32, @divExact(wide_reg.bitSize(), 16)),
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)),
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);
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try self.asmRegisterRegister(.vsqrtps, wide_reg, wide_reg);
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try self.asmRegisterRegisterImmediate(
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.vcvtps2ph,
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dst_reg,
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wide_reg,
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Immediate.u(0b1_00),
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);
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break :result dst_mcv;
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},
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else => null,
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} else null,
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32 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vsqrtss else .sqrtss,
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2...4 => if (self.hasFeature(.avx)) .vsqrtps else .sqrtps,
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5...8 => if (self.hasFeature(.avx)) .vsqrtps else null,
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else => null,
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},
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64 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vsqrtsd else .sqrtsd,
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2 => if (self.hasFeature(.avx)) .vsqrtpd else .sqrtpd,
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3...4 => if (self.hasFeature(.avx)) .vsqrtpd else null,
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else => null,
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},
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80, 128 => null,
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else => unreachable,
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},
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64 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) .vsqrtsd else .sqrtsd,
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2 => if (self.hasFeature(.avx)) .vsqrtpd else .sqrtpd,
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3...4 => if (self.hasFeature(.avx)) .vsqrtpd else null,
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else => null,
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},
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16, 80, 128 => null,
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else => unreachable,
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},
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else => unreachable,
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},
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else => unreachable,
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})) |tag| tag else return self.fail("TODO implement airSqrt for {}", .{
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ty.fmt(self.bin_file.options.module.?),
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});
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switch (tag) {
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.vsqrtss, .vsqrtsd => if (src_mcv.isRegister()) try self.asmRegisterRegisterRegister(
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tag,
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dst_reg,
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dst_reg,
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registerAlias(src_mcv.getReg().?, abi_size),
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) else try self.asmRegisterRegisterMemory(
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tag,
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dst_reg,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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),
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else => if (src_mcv.isRegister()) try self.asmRegisterRegister(
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tag,
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dst_reg,
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registerAlias(src_mcv.getReg().?, abi_size),
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) else try self.asmRegisterMemory(
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tag,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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),
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}
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return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
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})) |tag| tag else return self.fail("TODO implement airSqrt for {}", .{
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ty.fmt(self.bin_file.options.module.?),
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});
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switch (tag) {
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.vsqrtss, .vsqrtsd => if (src_mcv.isRegister()) try self.asmRegisterRegisterRegister(
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tag,
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dst_reg,
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dst_reg,
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registerAlias(src_mcv.getReg().?, abi_size),
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) else try self.asmRegisterRegisterMemory(
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tag,
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dst_reg,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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),
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else => if (src_mcv.isRegister()) try self.asmRegisterRegister(
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tag,
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dst_reg,
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registerAlias(src_mcv.getReg().?, abi_size),
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) else try self.asmRegisterMemory(
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tag,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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),
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}
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break :result dst_mcv;
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};
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return self.finishAir(inst, result, .{ un_op, .none, .none });
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}
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fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {
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@ -1047,9 +1047,9 @@ pub const table = [_]Entry{
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.{ .vsqrtps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x51 }, 0, .vex_128_wig, .avx },
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.{ .vsqrtps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x51 }, 0, .vex_256_wig, .avx },
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.{ .vsqrtsd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f }, 0, .vex_lig_wig, .avx },
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.{ .vsqrtsd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x51 }, 0, .vex_lig_wig, .avx },
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.{ .vsqrtss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f }, 0, .vex_lig_wig, .avx },
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.{ .vsqrtss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x51 }, 0, .vex_lig_wig, .avx },
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// F16C
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.{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128_w0, .f16c },
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@ -135,7 +135,6 @@ fn testSqrt() !void {
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test "@sqrt with vectors" {
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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