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std.Thread.Futex improvements (#11464)
* atomic: cache_line * Thread: Futex rewrite + more native platform support * Futex: tests compile * Futex: compiles and runs test * Futex: broadcast test * Futex: fix PosixImpl for tests * Futex: fix compile errors for bsd platforms * Futex: review changes + fix timeout=0 + more comments
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@ -1,5 +1,5 @@
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const std = @import("std.zig");
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const target = @import("builtin").target;
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const builtin = @import("builtin");
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pub const Ordering = std.builtin.AtomicOrder;
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@ -40,7 +40,7 @@ test "fence/compilerFence" {
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/// Signals to the processor that the caller is inside a busy-wait spin-loop.
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pub inline fn spinLoopHint() void {
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switch (target.cpu.arch) {
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switch (builtin.target.cpu.arch) {
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// No-op instruction that can hint to save (or share with a hardware-thread)
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// pipelining/power resources
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// https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
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@ -59,7 +59,7 @@ pub inline fn spinLoopHint() void {
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// `yield` was introduced in v6k but is also available on v6m.
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// https://www.keil.com/support/man/docs/armasm/armasm_dom1361289926796.htm
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.arm, .armeb, .thumb, .thumbeb => {
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const can_yield = comptime std.Target.arm.featureSetHasAny(target.cpu.features, .{
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const can_yield = comptime std.Target.arm.featureSetHasAny(builtin.target.cpu.features, .{
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.has_v6k, .has_v6m,
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});
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if (can_yield) {
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@ -80,3 +80,41 @@ test "spinLoopHint" {
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spinLoopHint();
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}
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}
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/// The estimated size of the CPU's cache line when atomically updating memory.
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/// Add this much padding or align to this boundary to avoid atomically-updated
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/// memory from forcing cache invalidations on near, but non-atomic, memory.
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///
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// https://en.wikipedia.org/wiki/False_sharing
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// https://github.com/golang/go/search?q=CacheLinePadSize
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pub const cache_line = switch (builtin.cpu.arch) {
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// x86_64: Starting from Intel's Sandy Bridge, the spatial prefetcher pulls in pairs of 64-byte cache lines at a time.
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// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
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//
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// aarch64: Some big.LITTLE ARM archs have "big" cores with 128-byte cache lines:
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// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
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// - https://cpufun.substack.com/p/more-m1-fun-hardware-information
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//
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// powerpc64: PPC has 128-byte cache lines
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
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.x86_64, .aarch64, .powerpc64 => 128,
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// These platforms reportedly have 32-byte cache lines
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
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.arm, .mips, .mips64, .riscv64 => 32,
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// This platform reportedly has 256-byte cache lines
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
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.s390x => 256,
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// Other x86 and WASM platforms have 64-byte cache lines.
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// The rest of the architectures are assumed to be similar.
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// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
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else => 64,
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};
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@ -36,6 +36,9 @@ pub const sem_t = ?*opaque {};
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pub extern "c" fn pthread_setname_np(thread: std.c.pthread_t, name: [*:0]const u8) E;
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pub extern "c" fn pthread_getname_np(thread: std.c.pthread_t, name: [*:0]u8, len: usize) E;
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pub extern "c" fn umtx_sleep(ptr: *const volatile c_int, value: c_int, timeout: c_int) c_int;
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pub extern "c" fn umtx_wakeup(ptr: *const volatile c_int, count: c_int) c_int;
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// See:
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// - https://gitweb.dragonflybsd.org/dragonfly.git/blob/HEAD:/include/unistd.h
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// - https://gitweb.dragonflybsd.org/dragonfly.git/blob/HEAD:/sys/sys/types.h
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@ -62,6 +62,46 @@ pub const sem_t = extern struct {
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_padding: u32,
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};
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// https://github.com/freebsd/freebsd-src/blob/main/sys/sys/umtx.h
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pub const UMTX_OP = enum(c_int) {
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LOCK = 0,
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UNLOCK = 1,
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WAIT = 2,
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WAKE = 3,
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MUTEX_TRYLOCK = 4,
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MUTEX_LOCK = 5,
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MUTEX_UNLOCK = 6,
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SET_CEILING = 7,
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CV_WAIT = 8,
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CV_SIGNAL = 9,
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CV_BROADCAST = 10,
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WAIT_UINT = 11,
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RW_RDLOCK = 12,
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RW_WRLOCK = 13,
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RW_UNLOCK = 14,
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WAIT_UINT_PRIVATE = 15,
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WAKE_PRIVATE = 16,
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MUTEX_WAIT = 17,
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MUTEX_WAKE = 18, // deprecated
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SEM_WAIT = 19, // deprecated
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SEM_WAKE = 20, // deprecated
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NWAKE_PRIVATE = 31,
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MUTEX_WAKE2 = 22,
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SEM2_WAIT = 23,
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SEM2_WAKE = 24,
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SHM = 25,
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ROBUST_LISTS = 26,
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};
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pub const UMTX_ABSTIME = 0x01;
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pub const _umtx_time = extern struct {
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_timeout: timespec,
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_flags: u32,
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_clockid: u32,
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};
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pub extern "c" fn _umtx_op(obj: usize, op: c_int, val: c_ulong, uaddr: usize, uaddr2: usize) c_int;
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pub const EAI = enum(c_int) {
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/// address family for hostname not supported
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ADDRFAMILY = 1,
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@ -45,6 +45,13 @@ pub extern "c" fn unveil(path: ?[*:0]const u8, permissions: ?[*:0]const u8) c_in
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pub extern "c" fn pthread_set_name_np(thread: std.c.pthread_t, name: [*:0]const u8) void;
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pub extern "c" fn pthread_get_name_np(thread: std.c.pthread_t, name: [*:0]u8, len: usize) void;
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// https://github.com/openbsd/src/blob/2207c4325726fdc5c4bcd0011af0fdf7d3dab137/sys/sys/futex.h
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pub const FUTEX_WAIT = 1;
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pub const FUTEX_WAKE = 2;
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pub const FUTEX_REQUEUE = 3;
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pub const FUTEX_PRIVATE_FLAG = 128;
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pub extern "c" fn futex(uaddr: ?*const volatile u32, op: c_int, val: c_int, timeout: ?*const timespec, uaddr2: ?*const volatile u32) c_int;
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pub const login_cap_t = extern struct {
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lc_class: ?[*:0]const u8,
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lc_cap: ?[*:0]const u8,
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