diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index 6ba81aecdd..cd2b90051d 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -5841,7 +5841,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
                     if (intrinsicsAllowed(self.target.*, ty)) {
                         const tag: Mir.Inst.Tag = switch (ty.tag()) {
                             .f32 => .movss,
-                            .f64 => .movsx,
+                            .f64 => .movsd,
                             else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
                         };
                         const ptr_size: Memory.PtrSize = switch (ty.tag()) {
diff --git a/src/arch/x86_64/Emit.zig b/src/arch/x86_64/Emit.zig
index 5b3b03e8ee..c490dea497 100644
--- a/src/arch/x86_64/Emit.zig
+++ b/src/arch/x86_64/Emit.zig
@@ -328,6 +328,16 @@ fn mirMovsx(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
             op1 = .{ .reg = data.rr.r1 };
             op2 = .{ .reg = data.rr.r2 };
         },
+        .rm_sib => {
+            const msib = emit.mir.extraData(Mir.MemorySib, data.rx.payload).data;
+            op1 = .{ .reg = data.rx.r1 };
+            op2 = .{ .mem = Mir.MemorySib.decode(msib) };
+        },
+        .rm_rip => {
+            const mrip = emit.mir.extraData(Mir.MemoryRip, data.rx.payload).data;
+            op1 = .{ .reg = data.rx.r1 };
+            op2 = .{ .mem = Mir.MemoryRip.decode(mrip) };
+        },
         else => unreachable, // TODO
     }