From e3352db9860ab14f7f5fc8a41f97305c049ab0fe Mon Sep 17 00:00:00 2001
From: pfg <pfg@pfg.pw>
Date: Tue, 4 Aug 2020 03:30:55 -0700
Subject: [PATCH] stage2: riscv correctly aligned functions

---
 src-self-hosted/type.zig | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src-self-hosted/type.zig b/src-self-hosted/type.zig
index 457a69ac6d..ca46caeaa8 100644
--- a/src-self-hosted/type.zig
+++ b/src-self-hosted/type.zig
@@ -510,13 +510,18 @@ pub const Type = extern union {
             .u8,
             .i8,
             .bool,
+            .array_u8_sentinel_0,
+            => return 1,
+
             .fn_noreturn_no_args, // represents machine code; not a pointer
             .fn_void_no_args, // represents machine code; not a pointer
             .fn_naked_noreturn_no_args, // represents machine code; not a pointer
             .fn_ccc_void_no_args, // represents machine code; not a pointer
             .function, // represents machine code; not a pointer
-            .array_u8_sentinel_0,
-            => return 1,
+            => return switch (target.cpu.arch) {
+                .riscv64 => 2,
+                else => 1,
+            },
 
             .i16, .u16 => return 2,
             .i32, .u32 => return 4,