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stage2 ARM: change binOp lowering mechanism to use Mir tags
The Air -> Mir correspondence is not 1:1, so this better represents what Mir insruction we actually want to generate.
This commit is contained in:
joachimschmidt557
parent
8b5d5f44e2
commit
e2e69803dc
@ -1196,7 +1196,7 @@ fn minMax(
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// register.
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assert(lhs_reg != rhs_reg); // see note above
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_ = try self.binOpRegister(.cmp_eq, null, .{ .register = lhs_reg }, .{ .register = rhs_reg }, lhs_ty, rhs_ty);
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_ = try self.binOpRegister(.cmp, null, .{ .register = lhs_reg }, .{ .register = rhs_reg }, lhs_ty, rhs_ty);
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const cond_choose_lhs: Condition = switch (tag) {
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.max => switch (int_info.signedness) {
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@ -2067,7 +2067,7 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
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/// Asserts that generating an instruction of that form is possible.
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fn binOpRegister(
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self: *Self,
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tag: Air.Inst.Tag,
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mir_tag: Mir.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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@ -2112,8 +2112,8 @@ fn binOpRegister(
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};
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defer self.register_manager.unfreezeRegs(&.{rhs_reg});
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const dest_reg = switch (tag) {
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.cmp_eq => .r0, // cmp has no destination regardless
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const dest_reg = switch (mir_tag) {
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.cmp => .r0, // cmp has no destination regardless
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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@ -2130,41 +2130,21 @@ fn binOpRegister(
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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.cmp_eq => .cmp,
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.mul => .mul,
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.bit_and,
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.bool_and,
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=> .@"and",
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.bit_or,
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.bool_or,
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=> .orr,
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.shl_exact => .lsl,
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.shr_exact => switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr,
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.unsigned => Mir.Inst.Tag.lsr,
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},
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.xor => .eor,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.sub,
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.cmp_eq,
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.bit_and,
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.bool_and,
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.bit_or,
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.bool_or,
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.xor,
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.cmp,
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.@"and",
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.orr,
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.eor,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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.shl_exact,
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.shr_exact,
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.lsl,
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.asr,
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.lsr,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rm = lhs_reg,
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@ -2200,7 +2180,7 @@ fn binOpRegister(
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/// Asserts that generating an instruction of that form is possible.
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fn binOpImmediate(
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self: *Self,
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tag: Air.Inst.Tag,
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mir_tag: Mir.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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@ -2230,8 +2210,8 @@ fn binOpImmediate(
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const dest_reg = switch (tag) {
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.cmp_eq => .r0, // cmp has no destination reg
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const dest_reg = switch (mir_tag) {
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.cmp => .r0, // cmp has no destination reg
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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@ -2250,40 +2230,21 @@ fn binOpImmediate(
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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.cmp_eq => .cmp,
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.bit_and,
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.bool_and,
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=> .@"and",
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.bit_or,
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.bool_or,
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=> .orr,
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.shl_exact => .lsl,
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.shr_exact => switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr,
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.unsigned => Mir.Inst.Tag.lsr,
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},
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.xor => .eor,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.sub,
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.cmp_eq,
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.bit_and,
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.bool_and,
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.bit_or,
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.bool_or,
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.xor,
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.cmp,
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.@"and",
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.orr,
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.eor,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs.immediate).?,
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} },
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.shl_exact,
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.shr_exact,
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.lsl,
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.asr,
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.lsr,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rm = lhs_reg,
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@ -2352,13 +2313,20 @@ fn binOp(
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else => unreachable,
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};
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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.cmp_eq => .cmp,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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return try self.binOpImmediate(mir_tag, maybe_inst, lhs, rhs, lhs_ty, false);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(tag, maybe_inst, rhs, lhs, rhs_ty, true);
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return try self.binOpImmediate(mir_tag, maybe_inst, rhs, lhs, rhs_ty, true);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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@ -2378,7 +2346,7 @@ fn binOp(
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// TODO add optimisations for multiplication
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// with immediates, for example a * 2 can be
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// lowered to a << 1
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(.mul, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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@ -2432,13 +2400,20 @@ fn binOp(
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const lhs_immediate_ok = lhs == .immediate and Instruction.Operand.fromU32(lhs.immediate) != null;
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const rhs_immediate_ok = rhs == .immediate and Instruction.Operand.fromU32(rhs.immediate) != null;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bit_and => .@"and",
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.bit_or => .orr,
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.xor => .eor,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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return try self.binOpImmediate(mir_tag, maybe_inst, lhs, rhs, lhs_ty, false);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(tag, maybe_inst, rhs, lhs, rhs_ty, true);
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return try self.binOpImmediate(mir_tag, maybe_inst, rhs, lhs, rhs_ty, true);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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@ -2457,10 +2432,19 @@ fn binOp(
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if (int_info.bits <= 32) {
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .lsl,
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.shr_exact => switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr,
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.unsigned => Mir.Inst.Tag.lsr,
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},
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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return try self.binOpImmediate(mir_tag, maybe_inst, lhs, rhs, lhs_ty, false);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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@ -2512,13 +2496,19 @@ fn binOp(
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const lhs_immediate_ok = lhs == .immediate;
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bool_and => .@"and",
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.bool_or => .orr,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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return try self.binOpImmediate(mir_tag, maybe_inst, lhs, rhs, lhs_ty, false);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(tag, maybe_inst, rhs, lhs, rhs_ty, true);
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return try self.binOpImmediate(mir_tag, maybe_inst, rhs, lhs, rhs_ty, true);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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},
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else => unreachable,
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@ -2537,7 +2527,7 @@ fn binOp(
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const elem_size = @intCast(u32, elem_ty.abiSize(self.target.*));
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if (elem_size == 1) {
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const base_tag: Air.Inst.Tag = switch (tag) {
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const base_tag: Mir.Inst.Tag = switch (tag) {
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.ptr_add => .add,
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.ptr_sub => .sub,
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else => unreachable,
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