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stage2 x86_64: add instruction encoder helper fn
This commit is contained in:
gracefu
parent
d4d21dd46d
commit
e1959ccd4e
@ -1,4 +1,8 @@
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const std = @import("std");
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const testing = std.testing;
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const mem = std.mem;
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const assert = std.debug.assert;
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const ArrayList = std.ArrayList;
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const Type = @import("../Type.zig");
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const DW = std.dwarf;
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@ -68,6 +72,11 @@ pub const Register = enum(u8) {
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return @truncate(u4, @enumToInt(self));
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}
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/// Like id, but only returns the lower 3 bits.
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pub fn low_id(self: Register) u3 {
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return @truncate(u3, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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return switch (self) {
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@ -136,6 +145,418 @@ pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8
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pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
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pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
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/// Represents an unencoded x86 instruction.
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///
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/// Roughly based on the table headings at http://ref.x86asm.net/coder64.html
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pub const Instruction = struct {
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/// Opcode prefix, needed for certain rare ops (e.g. MOVSS)
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opcode_prefix: ?u8 = null,
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/// One-byte primary opcode
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primary_opcode_1b: ?u8 = null,
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/// Two-byte primary opcode (always prefixed with 0f)
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primary_opcode_2b: ?u8 = null,
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// TODO: Support 3-byte opcodes
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/// Secondary opcode
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secondary_opcode: ?u8 = null,
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/// Opcode extension (to be placed in the ModR/M byte in place of reg)
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opcode_extension: ?u3 = null,
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/// Legacy prefixes to use with this instruction
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/// Most of the time, this field will be 0 and no prefixes are added.
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/// Otherwise, a prefix will be added for each field set.
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legacy_prefixes: LegacyPrefixes = .{},
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/// 64-bit operand size
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operand_size_64: bool = false,
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/// The opcode-reg field,
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/// stored in the 3 least significant bits of the opcode
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/// on certain instructions + REX if extended
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opcode_reg: ?Register = null,
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/// The reg field
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reg: ?Register = null,
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/// The mod + r/m field
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modrm: ?ModrmEffectiveAddress = null,
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/// Location of the 3rd operand, if applicable
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sib: ?SibEffectiveAddress = null,
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/// Number of bytes of immediate
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immediate_bytes: u8 = 0,
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/// The value of the immediate
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immediate: u64 = 0,
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/// See legacy_prefixes
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pub const LegacyPrefixes = packed struct {
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/// LOCK
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prefix_f0: bool = false,
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/// REPNZ, REPNE, REP, Scalar Double-precision
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prefix_f2: bool = false,
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/// REPZ, REPE, REP, Scalar Single-precision
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prefix_f3: bool = false,
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/// CS segment override or Branch not taken
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prefix_2e: bool = false,
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/// DS segment override
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prefix_36: bool = false,
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/// ES segment override
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prefix_26: bool = false,
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/// FS segment override
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prefix_64: bool = false,
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/// GS segment override
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prefix_65: bool = false,
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/// Branch taken
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prefix_3e: bool = false,
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/// Operand size override
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prefix_66: bool = false,
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/// Address size override
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prefix_67: bool = false,
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padding: u5 = 0,
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};
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/// Encodes an effective address for the Mod + R/M part of the ModR/M byte
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///
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/// Note that depending on the instruction, not all effective addresses are allowed.
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///
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/// Examples:
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/// eax: .reg = .eax
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/// [eax]: .mem = .eax
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/// [eax + 8]: .mem_disp = .{ .reg = .eax, .disp = 8 }
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/// [eax - 8]: .mem_disp = .{ .reg = .eax, .disp = -8 }
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/// [55]: .disp32 = 55
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pub const ModrmEffectiveAddress = union(enum) {
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reg: Register,
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mem: Register,
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mem_disp: struct {
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reg: Register,
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disp: i32,
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},
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disp32: u32,
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pub fn isExtended(self: @This()) bool {
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return switch (self) {
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.reg => |reg| reg.isExtended(),
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.mem => |memea| memea.isExtended(),
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.mem_disp => |mem_disp| mem_disp.reg.isExtended(),
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.disp32 => false,
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};
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}
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};
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/// Encodes an effective address for the SIB byte
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///
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/// Note that depending on the instruction, not all effective addresses are allowed.
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///
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/// Examples:
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/// [eax + ebx * 2]: .base_index = .{ .base = .eax, .index = .ebx, .scale = 2 }
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/// [eax]: .base_index = .{ .base = .eax, .index = null, .scale = 1 }
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/// [ebx * 2 + 256]: .index_disp = .{ .index = .ebx, .scale = 2, .disp = 256 }
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/// [[ebp] + ebx * 2 + 8]: .ebp_index_disp = .{ .index = .ebx, .scale = 2, .disp = 8 }
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pub const SibEffectiveAddress = union(enum) {
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base_index: struct {
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base: Register,
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index: ?Register,
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scale: u8, // 1, 2, 4, or 8
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},
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index_disp: struct {
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index: ?Register,
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scale: u8, // 1, 2, 4, or 8
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disp: u32,
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},
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ebp_index_disp: struct {
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index: ?Register,
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scale: u8, // 1, 2, 4, or 8
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disp: u32,
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},
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pub fn baseIsExtended(self: @This()) bool {
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return switch (self) {
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.base_index => |base_index| base_index.base.isExtended(),
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.index_disp, .ebp_index_disp => false,
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};
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}
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pub fn indexIsExtended(self: @This()) bool {
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return switch (self) {
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.base_index => |base_index| if (base_index.index) |idx| idx.isExtended() else false,
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.index_disp => |index_disp| if (index_disp.index) |idx| idx.isExtended() else false,
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.ebp_index_disp => |ebp_index_disp| if (ebp_index_disp.index) |idx| idx.isExtended() else false,
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};
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}
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};
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/// Writes the encoded Instruction to the code ArrayList
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pub fn encodeInto(inst: Instruction, code: *ArrayList(u8)) !void {
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// We need to write the following, in that order:
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// - Legacy prefixes (0 to 13 bytes)
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// - REX prefix (0 to 1 byte)
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// - Opcode (1, 2, or 3 bytes)
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// - ModR/M (0 or 1 byte)
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// - SIB (0 or 1 byte)
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// - Displacement (0, 1, 2, or 4 bytes)
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// - Immediate (0, 1, 2, 4, or 8 bytes)
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// By this calculation, an instruction could be up to 31 bytes long (will probably not happen)
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try code.ensureCapacity(code.items.len + 31);
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// Legacy prefixes
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if (@bitCast(u16, inst.legacy_prefixes) != 0) {
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// Hopefully this path isn't taken very often, so we'll do it the slow way for now
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// LOCK
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if (inst.legacy_prefixes.prefix_f0) code.appendAssumeCapacity(0xf0);
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// REPNZ, REPNE, REP, Scalar Double-precision
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if (inst.legacy_prefixes.prefix_f2) code.appendAssumeCapacity(0xf2);
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// REPZ, REPE, REP, Scalar Single-precision
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if (inst.legacy_prefixes.prefix_f3) code.appendAssumeCapacity(0xf3);
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// CS segment override or Branch not taken
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if (inst.legacy_prefixes.prefix_2e) code.appendAssumeCapacity(0x2e);
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// DS segment override
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if (inst.legacy_prefixes.prefix_36) code.appendAssumeCapacity(0x36);
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// ES segment override
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if (inst.legacy_prefixes.prefix_26) code.appendAssumeCapacity(0x26);
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// FS segment override
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if (inst.legacy_prefixes.prefix_64) code.appendAssumeCapacity(0x64);
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// GS segment override
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if (inst.legacy_prefixes.prefix_65) code.appendAssumeCapacity(0x65);
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// Branch taken
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if (inst.legacy_prefixes.prefix_3e) code.appendAssumeCapacity(0x3e);
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// Operand size override
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if (inst.legacy_prefixes.prefix_66) code.appendAssumeCapacity(0x66);
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// Address size override
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if (inst.legacy_prefixes.prefix_67) code.appendAssumeCapacity(0x67);
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}
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// REX prefix
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//
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// A REX prefix has the following form:
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// 0b0100_WRXB
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// 0100: fixed bits
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// W: stands for "wide", indicates that the instruction uses 64-bit operands.
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// R, X, and B each contain the 4th bit of a register
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// these have to be set when using registers 8-15.
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// R: stands for "reg", extends the reg field in the ModR/M byte.
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// X: stands for "index", extends the index field in the SIB byte.
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// B: stands for "base", extends either the r/m field in the ModR/M byte,
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// the base field in the SIB byte,
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// or the opcode reg field in the Opcode byte.
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{
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var value: u8 = 0x40;
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if (inst.opcode_reg) |opcode_reg| {
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if (opcode_reg.isExtended()) {
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value |= 0x1;
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}
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}
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if (inst.modrm) |modrm| {
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if (modrm.isExtended()) {
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value |= 0x1;
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}
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}
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if (inst.sib) |sib| {
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if (sib.baseIsExtended()) {
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value |= 0x1;
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}
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if (sib.indexIsExtended()) {
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value |= 0x2;
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}
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}
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if (inst.reg) |reg| {
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if (reg.isExtended()) {
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value |= 0x4;
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}
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}
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if (inst.operand_size_64) {
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value |= 0x8;
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}
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if (value != 0x40) {
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code.appendAssumeCapacity(value);
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}
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}
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// Opcode
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if (inst.primary_opcode_1b) |opcode| {
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var value = opcode;
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if (inst.opcode_reg) |opcode_reg| {
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value |= opcode_reg.low_id();
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}
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code.appendAssumeCapacity(value);
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} else if (inst.primary_opcode_2b) |opcode| {
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code.appendAssumeCapacity(0x0f);
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var value = opcode;
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if (inst.opcode_reg) |opcode_reg| {
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value |= opcode_reg.low_id();
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}
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code.appendAssumeCapacity(value);
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}
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var disp8: ?u8 = null;
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var disp16: ?u16 = null;
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var disp32: ?u32 = null;
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// ModR/M
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//
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// Example ModR/M byte:
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// c7: ModR/M byte that contains:
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// 11 000 111:
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// ^ ^ ^
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// mod | |
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// reg |
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// r/m
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// where mod = 11 indicates that both operands are registers,
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// reg = 000 indicates that the first operand is register EAX
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// r/m = 111 indicates that the second operand is register EDI (since mod = 11)
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if (inst.modrm != null or inst.reg != null or inst.opcode_extension != null) {
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var value: u8 = 0;
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// mod + rm
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if (inst.modrm) |modrm| {
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switch (modrm) {
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.reg => |reg| {
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value |= reg.low_id();
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value |= 0b11_000_000;
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},
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.mem => |memea| {
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assert(memea.low_id() != 4 and memea.low_id() != 5);
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value |= memea.low_id();
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// value |= 0b00_000_000;
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},
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.mem_disp => |mem_disp| {
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assert(mem_disp.reg.low_id() != 4);
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value |= mem_disp.reg.low_id();
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if (mem_disp.disp < 128) {
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// Use 1 byte of displacement
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value |= 0b01_000_000;
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disp8 = @bitCast(u8, @intCast(i8, mem_disp.disp));
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} else {
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// Use all 4 bytes of displacement
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value |= 0b10_000_000;
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disp32 = @bitCast(u32, mem_disp.disp);
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}
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},
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.disp32 => |d| {
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value |= 0b00_000_101;
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disp32 = d;
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},
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}
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}
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// reg
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if (inst.reg) |reg| {
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value |= @as(u8, reg.low_id()) << 3;
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} else if (inst.opcode_extension) |ext| {
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value |= @as(u8, ext) << 3;
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}
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code.appendAssumeCapacity(value);
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}
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// SIB
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{
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if (inst.sib) |sib| {
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return error.TODOSIBByteForX8664;
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}
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}
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// Displacement
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//
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// The size of the displacement depends on the instruction used and is very fragile.
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// The bytes are simply written in LE order.
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{
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// These writes won't fail because we ensured capacity earlier.
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if (disp8) |d|
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code.appendAssumeCapacity(d)
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else if (disp16) |d|
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mem.writeIntLittle(u16, code.addManyAsArrayAssumeCapacity(2), d)
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else if (disp32) |d|
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mem.writeIntLittle(u32, code.addManyAsArrayAssumeCapacity(4), d);
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}
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// Immediate
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//
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// The size of the immediate depends on the instruction used and is very fragile.
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// The bytes are simply written in LE order.
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{
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// These writes won't fail because we ensured capacity earlier.
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if (inst.immediate_bytes == 1)
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code.appendAssumeCapacity(@intCast(u8, inst.immediate))
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else if (inst.immediate_bytes == 2)
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mem.writeIntLittle(u16, code.addManyAsArrayAssumeCapacity(2), @intCast(u16, inst.immediate))
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else if (inst.immediate_bytes == 4)
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mem.writeIntLittle(u32, code.addManyAsArrayAssumeCapacity(4), @intCast(u32, inst.immediate))
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else if (inst.immediate_bytes == 8)
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mem.writeIntLittle(u64, code.addManyAsArrayAssumeCapacity(8), inst.immediate);
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}
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}
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};
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fn expectEncoded(inst: Instruction, expected: []const u8) !void {
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var code = ArrayList(u8).init(testing.allocator);
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defer code.deinit();
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try inst.encodeInto(&code);
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testing.expectEqualSlices(u8, expected, code.items);
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}
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test "x86_64 Instruction.encodeInto" {
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// simple integer multiplication
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// imul eax,edi
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// 0faf c7
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try expectEncoded(Instruction{
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.primary_opcode_2b = 0xaf, // imul
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.reg = .eax, // destination
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.modrm = .{ .reg = .edi }, // source
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}, &[_]u8{ 0x0f, 0xaf, 0xc7 });
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// simple mov
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// mov eax,edi
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// 89 f8
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try expectEncoded(Instruction{
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.primary_opcode_1b = 0x89, // mov (with rm as destination)
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.reg = .edi, // source
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.modrm = .{ .reg = .eax }, // destination
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}, &[_]u8{ 0x89, 0xf8 });
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// signed integer addition of 32-bit sign extended immediate to 64 bit register
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// add rcx, 2147483647
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//
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// Using the following opcode: REX.W + 81 /0 id, we expect the following encoding
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//
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// 48 : REX.W set for 64 bit operand (*r*cx)
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// 81 : opcode for "<arithmetic> with immediate"
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// c1 : id = rcx,
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// : c1 = 11 <-- mod = 11 indicates r/m is register (rcx)
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// : 000 <-- opcode_extension = 0 because opcode extension is /0. /0 specifies ADD
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// : 001 <-- 001 is rcx
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// ffffff7f : 2147483647
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try expectEncoded(Instruction{
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// REX.W +
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.operand_size_64 = true,
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// 81
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.primary_opcode_1b = 0x81,
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// /0
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.opcode_extension = 0,
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// rcx
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.modrm = .{ .reg = .rcx },
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// immediate
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.immediate_bytes = 4,
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.immediate = 2147483647,
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}, &[_]u8{ 0x48, 0x81, 0xc1, 0xff, 0xff, 0xff, 0x7f });
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}
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// TODO add these registers to the enum and populate dwarfLocOp
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// // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
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// RA = (16, "RA"),
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