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https://github.com/ziglang/zig.git
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x64: swap out register exceptions for freeze/unfreeze api
This commit is contained in:
Jakub Konka
parent
cfceec15e1
commit
e0b1170b67
@ -21,7 +21,7 @@ const Emit = @import("Emit.zig");
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const Liveness = @import("../../Liveness.zig");
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const Mir = @import("Mir.zig");
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const Module = @import("../../Module.zig");
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const RegisterManager = @import("../../register_manager.zig").RegisterManager;
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const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
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const Target = std.Target;
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const Type = @import("../../type.zig").Type;
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const TypedValue = @import("../../TypedValue.zig");
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@ -33,6 +33,8 @@ const InnerError = error{
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CodegenFail,
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};
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const RegisterManager = RegisterManagerFn(Self, Register, &callee_preserved_regs);
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gpa: Allocator,
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air: Air,
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liveness: Liveness,
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@ -73,7 +75,7 @@ branch_stack: *std.ArrayList(Branch),
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// Key is the block instruction
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blocks: std.AutoHashMapUnmanaged(Air.Inst.Index, BlockData) = .{},
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register_manager: RegisterManager(Self, Register, &callee_preserved_regs) = .{},
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register_manager: RegisterManager = .{},
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/// Maps offset to what is stored there.
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stack: std.AutoHashMapUnmanaged(u32, StackAllocation) = .{},
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@ -169,6 +171,24 @@ pub const MCValue = union(enum) {
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else => false,
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};
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}
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fn freezeIfRegister(mcv: MCValue, mgr: *RegisterManager) void {
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switch (mcv) {
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.register => |reg| {
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mgr.freezeRegs(&.{reg});
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},
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else => {},
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}
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}
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fn unfreezeIfRegister(mcv: MCValue, mgr: *RegisterManager) void {
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switch (mcv) {
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.register => |reg| {
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mgr.unfreezeRegs(&.{reg});
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},
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else => {},
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}
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}
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};
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const Branch = struct {
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@ -836,20 +856,6 @@ fn copyToNewRegister(self: *Self, reg_owner: Air.Inst.Index, ty: Type, mcv: MCVa
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return MCValue{ .register = reg };
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}
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/// Like `copyToNewRegister` but allows to specify a list of excluded registers which
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/// will not be selected for allocation. This can be done via `exceptions` slice.
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fn copyToNewRegisterWithExceptions(
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self: *Self,
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reg_owner: Air.Inst.Index,
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ty: Type,
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mcv: MCValue,
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exceptions: []const Register,
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) !MCValue {
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const reg = try self.register_manager.allocReg(reg_owner, exceptions);
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try self.genSetReg(ty, reg, mcv);
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return MCValue{ .register = reg };
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}
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fn airAlloc(self: *Self, inst: Air.Inst.Index) !void {
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const stack_offset = try self.allocMemPtr(inst);
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return self.finishAir(inst, .{ .ptr_stack_offset = @intCast(i32, stack_offset) }, .{ .none, .none, .none });
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@ -897,8 +903,9 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
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return self.fail("TODO implement intCast for abi sizes larger than 8", .{});
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}
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if (operand.isRegister()) self.register_manager.freezeRegs(&.{operand.register});
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defer if (operand.isRegister()) self.register_manager.unfreezeRegs(&.{operand.register});
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operand.freezeIfRegister(&self.register_manager);
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defer operand.unfreezeIfRegister(&self.register_manager);
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break :blk try self.copyToNewRegister(inst, dest_ty, operand);
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};
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@ -1366,8 +1373,7 @@ fn airPtrSlicePtrPtr(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn elemOffset(self: *Self, index_ty: Type, index: MCValue, elem_size: u64) !Register {
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const reg = try self.register_manager.allocReg(null, &.{});
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try self.genSetReg(index_ty, reg, index);
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const reg = try self.copyToTmpRegister(index_ty, index);
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try self.genIMulOpMir(index_ty, .{ .register = reg }, .{ .immediate = elem_size });
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return reg;
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}
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@ -1376,16 +1382,26 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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const is_volatile = false; // TODO
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (!is_volatile and self.liveness.isUnused(inst)) .dead else result: {
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const slice_mcv = try self.resolveInst(bin_op.lhs);
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const slice_ty = self.air.typeOf(bin_op.lhs);
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const slice_mcv = try self.resolveInst(bin_op.lhs);
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slice_mcv.freezeIfRegister(&self.register_manager);
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defer slice_mcv.unfreezeIfRegister(&self.register_manager);
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const elem_ty = slice_ty.childType();
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const elem_size = elem_ty.abiSize(self.target.*);
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var buf: Type.SlicePtrFieldTypeBuffer = undefined;
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const slice_ptr_field_type = slice_ty.slicePtrFieldType(&buf);
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const index_ty = self.air.typeOf(bin_op.rhs);
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const index_mcv = try self.resolveInst(bin_op.rhs);
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index_mcv.freezeIfRegister(&self.register_manager);
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defer index_mcv.unfreezeIfRegister(&self.register_manager);
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const offset_reg = try self.elemOffset(index_ty, index_mcv, elem_size);
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const addr_reg = try self.register_manager.allocReg(null, &.{offset_reg});
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self.register_manager.freezeRegs(&.{offset_reg});
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defer self.register_manager.unfreezeRegs(&.{offset_reg});
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const addr_reg = try self.register_manager.allocReg(null, &.{});
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switch (slice_mcv) {
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.stack_offset => |off| {
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// mov reg, [rbp - 8]
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@ -1401,7 +1417,7 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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},
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else => return self.fail("TODO implement slice_elem_val when slice is {}", .{slice_mcv}),
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}
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// TODO we could allocate register here, but need to except addr register and potentially
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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const dst_mcv = try self.allocRegOrMem(inst, false);
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try self.genBinMathOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg.to64() }, .{
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@ -1427,14 +1443,23 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const array_ty = self.air.typeOf(bin_op.lhs);
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const array = try self.resolveInst(bin_op.lhs);
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const array_abi_size = array_ty.abiSize(self.target.*);
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const array = try self.resolveInst(bin_op.lhs);
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array.freezeIfRegister(&self.register_manager);
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defer array.unfreezeIfRegister(&self.register_manager);
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const elem_ty = array_ty.childType();
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const elem_abi_size = elem_ty.abiSize(self.target.*);
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const index_ty = self.air.typeOf(bin_op.rhs);
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const index = try self.resolveInst(bin_op.rhs);
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index.freezeIfRegister(&self.register_manager);
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defer index.unfreezeIfRegister(&self.register_manager);
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const offset_reg = try self.elemOffset(index_ty, index, elem_abi_size);
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const addr_reg = try self.register_manager.allocReg(null, &.{offset_reg});
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self.register_manager.freezeRegs(&.{offset_reg});
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defer self.register_manager.unfreezeRegs(&.{offset_reg});
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const addr_reg = try self.register_manager.allocReg(null, &.{});
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switch (array) {
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.stack_offset => |off| {
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// lea reg, [rbp]
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@ -1449,7 +1474,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
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},
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else => return self.fail("TODO implement array_elem_val when array is {}", .{array}),
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}
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// TODO we could allocate register here, but need to except addr register and potentially
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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const dst_mcv = try self.allocRegOrMem(inst, false);
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try self.genBinMathOpMir(.add, array_ty, .{ .register = addr_reg.to64() }, .{ .register = offset_reg.to64() });
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@ -1475,12 +1500,17 @@ fn airPtrElemPtr(self: *Self, inst: Air.Inst.Index) !void {
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const ptr_ty = self.air.typeOf(extra.lhs);
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const ptr = try self.resolveInst(extra.lhs);
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ptr.freezeIfRegister(&self.register_manager);
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defer ptr.unfreezeIfRegister(&self.register_manager);
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const elem_ty = ptr_ty.elemType2();
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const elem_abi_size = elem_ty.abiSize(self.target.*);
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const index_ty = self.air.typeOf(extra.rhs);
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const index = try self.resolveInst(extra.rhs);
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const offset_reg = try self.elemOffset(index_ty, index, elem_abi_size);
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index.freezeIfRegister(&self.register_manager);
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defer index.unfreezeIfRegister(&self.register_manager);
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const offset_reg = try self.elemOffset(index_ty, index, elem_abi_size);
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self.register_manager.freezeRegs(&.{offset_reg});
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defer self.register_manager.unfreezeRegs(&.{offset_reg});
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@ -1587,6 +1617,9 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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return self.fail("TODO implement loading from MCValue.embedded_in_code", .{});
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},
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.register => |reg| {
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self.register_manager.freezeRegs(&.{reg});
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defer self.register_manager.unfreezeRegs(&.{reg});
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switch (dst_mcv) {
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.dead => unreachable,
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.undef => unreachable,
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@ -1607,16 +1640,15 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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},
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.stack_offset => |off| {
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if (abi_size <= 8) {
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const tmp_reg = try self.register_manager.allocReg(null, &.{reg});
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const tmp_reg = try self.register_manager.allocReg(null, &.{});
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try self.load(.{ .register = tmp_reg }, ptr, ptr_ty);
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return self.genSetStack(elem_ty, off, MCValue{ .register = tmp_reg });
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}
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const regs = try self.register_manager.allocRegs(
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3,
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.{ null, null, null },
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&.{ reg, .rax, .rcx },
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);
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self.register_manager.freezeRegs(&.{ .rax, .rcx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx });
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null }, &.{});
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const addr_reg = regs[0];
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const count_reg = regs[1];
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const tmp_reg = regs[2];
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@ -1634,7 +1666,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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try self.register_manager.getReg(.rcx, null);
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// TODO allow for abi size to be u64
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try self.genSetReg(Type.initTag(.u32), count_reg, .{ .immediate = @intCast(u32, abi_size) });
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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return self.genInlineMemcpy(
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-(off + @intCast(i32, abi_size)),
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@ -1786,8 +1818,8 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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// TODO: in case the address fits in an imm32 we can use [ds:imm32]
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// instead of wasting an instruction copying the address to a register
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if (value.isRegister()) self.register_manager.freezeRegs(&.{value.register});
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defer if (value.isRegister()) self.register_manager.unfreezeRegs(&.{value.register});
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value.freezeIfRegister(&self.register_manager);
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defer value.unfreezeIfRegister(&self.register_manager);
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const addr_reg = try self.copyToTmpRegister(ptr_ty, .{ .immediate = addr });
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// to get the actual address of the value we want to modify we have to go through the GOT
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@ -2012,22 +2044,16 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
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}
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} else {
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if (lhs.isMemory()) {
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dst_mcv = if (rhs.isRegister())
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// If the allocated register is the same as the rhs register, don't allocate that one
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// and instead spill a subsequent one. Otherwise, this can result in a miscompilation
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// in the presence of several binary operations performed in a single block.
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try self.copyToNewRegisterWithExceptions(inst, dst_ty, lhs, &.{rhs.register})
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else
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try self.copyToNewRegister(inst, dst_ty, lhs);
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rhs.freezeIfRegister(&self.register_manager);
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defer rhs.unfreezeIfRegister(&self.register_manager);
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dst_mcv = try self.copyToNewRegister(inst, dst_ty, lhs);
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src_mcv = rhs;
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} else {
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dst_mcv = if (lhs.isRegister())
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// If the allocated register is the same as the rhs register, don't allocate that one
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// and instead spill a subsequent one. Otherwise, this can result in a miscompilation
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// in the presence of several binary operations performed in a single block.
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try self.copyToNewRegisterWithExceptions(inst, dst_ty, rhs, &.{lhs.register})
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else
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try self.copyToNewRegister(inst, dst_ty, rhs);
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lhs.freezeIfRegister(&self.register_manager);
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defer lhs.unfreezeIfRegister(&self.register_manager);
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dst_mcv = try self.copyToNewRegister(inst, dst_ty, rhs);
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src_mcv = lhs;
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}
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}
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@ -2039,7 +2065,11 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
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switch (src_mcv) {
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.immediate => |imm| {
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if (imm > math.maxInt(u31)) {
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src_mcv = MCValue{ .register = try self.copyToTmpRegister(Type.initTag(.u64), src_mcv) };
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dst_mcv.freezeIfRegister(&self.register_manager);
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defer dst_mcv.unfreezeIfRegister(&self.register_manager);
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const tmp_reg = try self.copyToTmpRegister(Type.u64, src_mcv);
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src_mcv = MCValue{ .register = tmp_reg };
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}
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},
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else => {},
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@ -2901,6 +2931,8 @@ fn airIsNullPtr(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand_ptr = try self.resolveInst(un_op);
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operand_ptr.freezeIfRegister(&self.register_manager);
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defer operand_ptr.unfreezeIfRegister(&self.register_manager);
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const operand: MCValue = blk: {
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if (self.reuseOperand(inst, un_op, 0, operand_ptr)) {
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// The MCValue that holds the pointer can be re-used as the value.
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@ -2930,6 +2962,8 @@ fn airIsNonNullPtr(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand_ptr = try self.resolveInst(un_op);
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operand_ptr.freezeIfRegister(&self.register_manager);
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defer operand_ptr.unfreezeIfRegister(&self.register_manager);
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const operand: MCValue = blk: {
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if (self.reuseOperand(inst, un_op, 0, operand_ptr)) {
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// The MCValue that holds the pointer can be re-used as the value.
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@ -2959,6 +2993,8 @@ fn airIsErrPtr(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand_ptr = try self.resolveInst(un_op);
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operand_ptr.freezeIfRegister(&self.register_manager);
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defer operand_ptr.unfreezeIfRegister(&self.register_manager);
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const operand: MCValue = blk: {
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if (self.reuseOperand(inst, un_op, 0, operand_ptr)) {
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// The MCValue that holds the pointer can be re-used as the value.
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@ -2988,6 +3024,8 @@ fn airIsNonErrPtr(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand_ptr = try self.resolveInst(un_op);
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operand_ptr.freezeIfRegister(&self.register_manager);
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defer operand_ptr.unfreezeIfRegister(&self.register_manager);
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const operand: MCValue = blk: {
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if (self.reuseOperand(inst, un_op, 0, operand_ptr)) {
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// The MCValue that holds the pointer can be re-used as the value.
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@ -3345,7 +3383,10 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
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}
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null }, &.{ .rax, .rcx });
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self.register_manager.freezeRegs(&.{ .rax, .rcx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx });
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null }, &.{});
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const addr_reg = regs[0];
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const count_reg = regs[1];
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const tmp_reg = regs[2];
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@ -3363,7 +3404,7 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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});
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// TODO allow for abi_size to be u64
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try self.genSetReg(Type.initTag(.u32), count_reg, .{ .immediate = @intCast(u32, abi_size) });
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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try self.genInlineMemcpy(
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-(stack_offset + @intCast(i32, abi_size)),
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.rsp,
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@ -3510,7 +3551,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerErro
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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}
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null }, &.{ .rax, .rcx, .rbp });
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self.register_manager.freezeRegs(&.{ .rax, .rcx, .rbp });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx, .rbp });
|
||||
|
||||
const regs = try self.register_manager.allocRegs(3, .{ null, null, null }, &.{});
|
||||
const addr_reg = regs[0];
|
||||
const count_reg = regs[1];
|
||||
const tmp_reg = regs[2];
|
||||
@ -3528,7 +3572,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerErro
|
||||
});
|
||||
|
||||
// TODO allow for abi_size to be u64
|
||||
try self.genSetReg(Type.initTag(.u32), count_reg, .{ .immediate = @intCast(u32, abi_size) });
|
||||
try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
|
||||
|
||||
return self.genInlineMemcpy(
|
||||
-(stack_offset + @intCast(i32, abi_size)),
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user