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x64: clean up loadMemPtrIntoRegister abstraction
This commit is contained in:
Jakub Konka
parent
12cdb36c5b
commit
decc90e0e7
@ -2032,42 +2032,44 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
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self.register_manager.freezeRegs(&.{offset_reg});
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defer self.register_manager.unfreezeRegs(&.{offset_reg});
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const addr_reg = blk: {
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const off = inner: {
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switch (array) {
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.register => {
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const off = @intCast(i32, try self.allocMem(
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inst,
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@intCast(u32, array_ty.abiSize(self.target.*)),
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array_ty.abiAlignment(self.target.*),
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));
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try self.genSetStack(array_ty, off, array, .{});
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break :inner off;
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},
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.stack_offset => |off| {
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break :inner off;
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},
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.memory,
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.got_load,
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.direct_load,
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=> {
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break :blk try self.loadMemPtrIntoRegister(Type.usize, array);
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},
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else => return self.fail("TODO implement array_elem_val when array is {}", .{array}),
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}
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};
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const addr_reg = try self.register_manager.allocReg(null);
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// lea reg, [rbp]
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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break :blk addr_reg.to64();
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};
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const addr_reg = try self.register_manager.allocReg(null);
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switch (array) {
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.register => {
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const off = @intCast(i32, try self.allocMem(
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inst,
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@intCast(u32, array_ty.abiSize(self.target.*)),
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array_ty.abiAlignment(self.target.*),
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));
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try self.genSetStack(array_ty, off, array, .{});
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// lea reg, [rbp]
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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},
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.stack_offset => |off| {
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// lea reg, [rbp]
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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},
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.memory,
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.got_load,
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.direct_load,
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=> {
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try self.loadMemPtrIntoRegister(addr_reg, Type.usize, array);
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},
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else => return self.fail("TODO implement array_elem_val when array is {}", .{array}),
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}
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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@ -2373,7 +2375,7 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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fn loadMemPtrIntoRegister(self: *Self, ptr_ty: Type, ptr: MCValue) InnerError!Register {
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fn loadMemPtrIntoRegister(self: *Self, reg: Register, ptr_ty: Type, ptr: MCValue) InnerError!void {
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switch (ptr) {
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.got_load,
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.direct_load,
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@ -2383,11 +2385,10 @@ fn loadMemPtrIntoRegister(self: *Self, ptr_ty: Type, ptr: MCValue) InnerError!Re
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.direct_load => 0b01,
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else => unreachable,
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};
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const reg = try self.register_manager.allocReg(null);
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_ = try self.addInst(.{
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.tag = .lea_pie,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.reg1 = registerAlias(reg, @intCast(u32, ptr_ty.abiSize(self.target.*))),
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.flags = flags,
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}).encode(),
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.data = .{
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@ -2397,13 +2398,11 @@ fn loadMemPtrIntoRegister(self: *Self, ptr_ty: Type, ptr: MCValue) InnerError!Re
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},
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},
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});
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return reg.to64();
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},
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.memory => |addr| {
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// TODO: in case the address fits in an imm32 we can use [ds:imm32]
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// instead of wasting an instruction copying the address to a register
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const reg = try self.copyToTmpRegister(ptr_ty, .{ .immediate = addr });
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return reg.to64();
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try self.genSetReg(ptr_ty, reg, .{ .immediate = addr });
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},
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else => unreachable,
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}
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@ -2503,7 +2502,11 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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.data = .{ .imm = 0 },
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});
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},
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.stack_offset => {
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.got_load,
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.direct_load,
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.memory,
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.stack_offset,
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=> {
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if (abi_size <= 8) {
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const tmp_reg = try self.copyToTmpRegister(value_ty, value);
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return self.store(ptr, .{ .register = tmp_reg }, ptr_ty, value_ty);
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@ -2526,7 +2529,8 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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value.freezeIfRegister(&self.register_manager);
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defer value.unfreezeIfRegister(&self.register_manager);
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const addr_reg = try self.loadMemPtrIntoRegister(ptr_ty, ptr);
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const addr_reg = try self.register_manager.allocReg(null);
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try self.loadMemPtrIntoRegister(addr_reg, ptr_ty, ptr);
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// to get the actual address of the value we want to modify we have to go through the GOT
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// mov reg, [reg]
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@ -4678,43 +4682,38 @@ fn genInlineMemcpy(self: *Self, stack_offset: i32, ty: Type, val: MCValue, opts:
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if (opts.dest_stack_base) |reg| self.register_manager.freezeRegs(&.{reg});
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defer if (opts.dest_stack_base) |reg| self.register_manager.unfreezeRegs(&.{reg});
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const addr_reg: Register = blk: {
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switch (val) {
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.memory,
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.direct_load,
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.got_load,
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=> {
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break :blk try self.loadMemPtrIntoRegister(Type.usize, val);
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},
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.ptr_stack_offset, .stack_offset => |off| {
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const addr_reg = (try self.register_manager.allocReg(null)).to64();
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg,
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.reg2 = opts.source_stack_base orelse .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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break :blk addr_reg;
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},
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.register => |reg| {
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const addr_reg = try self.register_manager.allocReg(null);
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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break :blk addr_reg.to64();
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},
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else => {
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return self.fail("TODO implement memcpy for setting stack from {}", .{val});
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},
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}
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};
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const addr_reg = try self.register_manager.allocReg(null);
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switch (val) {
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.memory,
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.direct_load,
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.got_load,
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=> {
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try self.loadMemPtrIntoRegister(addr_reg, Type.usize, val);
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},
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.ptr_stack_offset, .stack_offset => |off| {
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg2 = opts.source_stack_base orelse .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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},
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.register => |reg| {
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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},
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else => {
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return self.fail("TODO implement memcpy for setting stack from {}", .{val});
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},
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}
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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@ -401,7 +401,6 @@ test "tagged union with no payloads" {
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}
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test "union with only 1 field casted to its enum type" {
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
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@ -841,7 +840,6 @@ test "@unionInit can modify a union type" {
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}
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test "@unionInit can modify a pointer value" {
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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