diff --git a/lib/std/debug/Dwarf.zig b/lib/std/debug/Dwarf.zig
index fd0683d156..29091f2a53 100644
--- a/lib/std/debug/Dwarf.zig
+++ b/lib/std/debug/Dwarf.zig
@@ -1431,6 +1431,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
     return switch (arch) {
         .aarch64, .aarch64_be => 32,
         .arm, .armeb, .thumb, .thumbeb => 15,
+        .csky => 64,
         .hexagon => 76,
         .lanai => 2,
         .loongarch32, .loongarch64 => 64,
@@ -1450,6 +1451,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
     return switch (arch) {
         .aarch64, .aarch64_be => 29,
         .arm, .armeb, .thumb, .thumbeb => 11,
+        .csky => 14,
         .hexagon => 30,
         .lanai => 5,
         .loongarch32, .loongarch64 => 22,
@@ -1469,6 +1471,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
     return switch (arch) {
         .aarch64, .aarch64_be => 31,
         .arm, .armeb, .thumb, .thumbeb => 13,
+        .csky => 14,
         .hexagon => 29,
         .lanai => 4,
         .loongarch32, .loongarch64 => 3,
diff --git a/lib/std/debug/SelfInfo/Elf.zig b/lib/std/debug/SelfInfo/Elf.zig
index bee04a5eef..4f3fbe9177 100644
--- a/lib/std/debug/SelfInfo/Elf.zig
+++ b/lib/std/debug/SelfInfo/Elf.zig
@@ -101,10 +101,11 @@ pub const can_unwind: bool = s: {
             .x86,
             .x86_64,
         },
-        // Not supported yet: arc, arm/armeb/thumb/thumbeb, csky, m68k, or1k, xtensa
+        // Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, or1k, xtensa
         .linux => &.{
             .aarch64,
             .aarch64_be,
+            .csky,
             .loongarch64,
             .mips,
             .mipsel,
diff --git a/lib/std/debug/cpu_context.zig b/lib/std/debug/cpu_context.zig
index b3c348df90..eb255d20ac 100644
--- a/lib/std/debug/cpu_context.zig
+++ b/lib/std/debug/cpu_context.zig
@@ -6,6 +6,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
 else switch (native_arch) {
     .aarch64, .aarch64_be => Aarch64,
     .arm, .armeb, .thumb, .thumbeb => Arm,
+    .csky => Csky,
     .hexagon => Hexagon,
     .lanai => Lanai,
     .loongarch32, .loongarch64 => LoongArch,
@@ -74,6 +75,13 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
             .sp = uc.mcontext.sp,
             .pc = uc.mcontext.pc,
         },
+        .csky => .{
+            .r = uc.mcontext.r0_13 ++
+                [_]u32{ uc.mcontext.r14, uc.mcontext.r15 } ++
+                uc.mcontext.r16_30 ++
+                [_]u32{uc.mcontext.r31},
+            .pc = uc.mcontext.pc,
+        },
         .hexagon, .loongarch32, .loongarch64, .mips, .mipsel, .mips64, .mips64el, .or1k => .{
             .r = uc.mcontext.r,
             .pc = uc.mcontext.pc,
@@ -433,6 +441,37 @@ const Aarch64 = extern struct {
     }
 };
 
+/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
+const Csky = extern struct {
+    /// The numbered general-purpose registers r0 - r31.
+    r: [32]u32,
+    pc: u32,
+
+    pub inline fn current() Csky {
+        var ctx: Csky = undefined;
+        asm volatile (
+            \\ stm r0-r31, (t0)
+            \\ grs t1, 1f
+            \\1:
+            \\ st32.w t1, (t0, 128)
+            :
+            : [ctx] "{r12}" (&ctx),
+            : .{ .r13 = true, .memory = true });
+        return ctx;
+    }
+
+    pub fn dwarfRegisterBytes(ctx: *Csky, register_num: u16) DwarfRegisterError![]u8 {
+        switch (register_num) {
+            0...31 => return @ptrCast(&ctx.r[register_num]),
+            64 => return @ptrCast(&ctx.pc),
+
+            32...63 => return error.UnsupportedRegister, // f0 - f31
+
+            else => return error.InvalidRegister,
+        }
+    }
+};
+
 /// This is an `extern struct` so that inline assembly in `current` can use field offsets.
 const Hexagon = extern struct {
     /// The numbered general-purpose registers r0 - r31.