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stage2 AArch64: move remaining operations out of binOp
This commit is contained in:
joachimschmidt557
parent
3800bb538a
commit
dd62d5941e
@ -1401,7 +1401,8 @@ fn allocRegs(
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for (read_args) |arg, i| {
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv == .register) {
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arg.reg.* = mcv.register;
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const raw_reg = mcv.register;
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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} else {
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const track_inst: ?Air.Inst.Index = switch (arg.bind) {
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.inst => |inst| Air.refToIndex(inst).?,
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@ -1418,7 +1419,8 @@ fn allocRegs(
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const operand_mapping = reuse_metadata.?.operand_mapping;
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const arg = write_args[0];
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if (arg.bind == .reg) {
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arg.reg.* = arg.bind.reg;
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const raw_reg = arg.bind.reg;
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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} else {
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reuse_operand: for (read_args) |read_arg, i| {
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if (read_arg.bind == .inst) {
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@ -1428,7 +1430,8 @@ fn allocRegs(
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std.meta.eql(arg.class, read_arg.class) and
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self.reuseOperand(inst, operand, operand_mapping[i], mcv))
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{
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arg.reg.* = mcv.register;
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const raw_reg = mcv.register;
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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write_locks[0] = null;
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reused_read_arg = i;
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break :reuse_operand;
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@ -1443,7 +1446,8 @@ fn allocRegs(
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} else {
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for (write_args) |arg, i| {
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if (arg.bind == .reg) {
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arg.reg.* = arg.bind.reg;
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const raw_reg = arg.bind.reg;
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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} else {
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const raw_reg = try self.register_manager.allocReg(null, arg.class);
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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@ -1887,189 +1891,6 @@ const BinOpMetadata = struct {
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rhs: Air.Inst.Ref,
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};
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/// For all your binary operation needs, this function will generate
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/// the corresponding Mir instruction(s). Returns the location of the
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/// result.
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///
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/// If the binary operation itself happens to be an Air instruction,
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/// pass the corresponding index in the inst parameter. That helps
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/// this function do stuff like reusing operands.
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///
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/// This function does not do any lowering to Mir itself, but instead
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/// looks at the lhs and rhs and determines which kind of lowering
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/// would be best suitable and then delegates the lowering to other
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/// functions.
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fn binOp(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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metadata: ?BinOpMetadata,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (tag) {
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.addwrap,
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.subwrap,
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.mulwrap,
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=> {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.addwrap => .add,
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.subwrap => .sub,
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.mulwrap => .mul,
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else => unreachable,
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};
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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ReadArg.Bind{ .mcv = lhs };
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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// Generate an add/sub/mul
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const maybe_inst: ?Air.Inst.Index = if (metadata) |md| md.inst else null;
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const result = try self.addSub(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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// Truncate if necessary
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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const result_reg = result.register;
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else {
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return self.fail("TODO binary operations on integers > u64/i64", .{});
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}
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},
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else => unreachable,
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}
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},
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.bit_and,
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.bit_or,
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.xor,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// TODO implement bitwise operations with immediates
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bit_and => .and_shifted_register,
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.bit_or => .orr_shifted_register,
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.xor => .eor_shifted_register,
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else => unreachable,
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};
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return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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},
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.shl_exact,
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.shr_exact,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .lsl_register,
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.shr_exact => switch (int_info.signedness) {
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.signed => Mir.Inst.Tag.asr_register,
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.unsigned => Mir.Inst.Tag.lsr_register,
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},
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else => unreachable,
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};
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const mir_tag_immediate: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .lsl_immediate,
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.shr_exact => switch (int_info.signedness) {
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.signed => Mir.Inst.Tag.asr_immediate,
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.unsigned => Mir.Inst.Tag.lsr_immediate,
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},
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(mir_tag_immediate, lhs, rhs, lhs_ty, false, metadata);
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} else {
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return try self.binOpRegister(mir_tag_register, lhs, rhs, lhs_ty, rhs_ty, metadata);
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}
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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},
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.shl,
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.shr,
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=> {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.shl => .shl_exact,
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.shr => .shr_exact,
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else => unreachable,
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};
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// Generate a shl_exact/shr_exact
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const result = try self.binOp(base_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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// Truncate if necessary
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switch (tag) {
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.shr => return result,
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.shl => switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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const result_reg = result.register;
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else {
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return self.fail("TODO binary operations on integers > u64/i64", .{});
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}
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},
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else => unreachable,
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},
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else => unreachable,
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}
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},
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.bool_and,
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.bool_or,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Bool => {
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assert(lhs != .immediate); // should have been handled by Sema
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assert(rhs != .immediate); // should have been handled by Sema
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.bool_and => .and_shifted_register,
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.bool_or => .orr_shifted_register,
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else => unreachable,
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};
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return try self.binOpRegister(mir_tag_register, lhs, rhs, lhs_ty, rhs_ty, metadata);
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},
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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fn addSub(
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self: *Self,
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tag: Air.Inst.Tag,
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@ -2369,6 +2190,189 @@ fn modulo(
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}
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}
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fn wrappingArithmetic(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// Generate an add/sub/mul
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const result: MCValue = switch (tag) {
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.addwrap => try self.addSub(.add, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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.subwrap => try self.addSub(.sub, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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.mulwrap => try self.mul(lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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else => unreachable,
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};
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// Truncate if necessary
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const result_reg = result.register;
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else {
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return self.fail("TODO binary operations on integers > u64/i64", .{});
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}
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},
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else => unreachable,
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}
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}
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fn bitwise(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// TODO implement bitwise operations with immediates
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bit_and => .and_shifted_register,
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.bit_or => .orr_shifted_register,
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.xor => .eor_shifted_register,
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else => unreachable,
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};
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return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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}
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fn shiftExact(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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_ = rhs_ty;
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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const rhs_immediate = try rhs_bind.resolveToImmediate(self);
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .lsl_register,
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.shr_exact => switch (int_info.signedness) {
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.signed => Mir.Inst.Tag.asr_register,
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.unsigned => Mir.Inst.Tag.lsr_register,
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},
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else => unreachable,
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};
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const mir_tag_immediate: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .lsl_immediate,
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.shr_exact => switch (int_info.signedness) {
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.signed => Mir.Inst.Tag.asr_immediate,
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.unsigned => Mir.Inst.Tag.lsr_immediate,
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},
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else => unreachable,
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};
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if (rhs_immediate) |imm| {
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return try self.binOpImmediateNew(mir_tag_immediate, lhs_bind, imm, lhs_ty, false, maybe_inst);
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} else {
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// We intentionally pass lhs_ty here in order to
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// prevent using the 32-bit register alias when
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// lhs_ty is > 32 bits.
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return try self.binOpRegisterNew(mir_tag_register, lhs_bind, rhs_bind, lhs_ty, lhs_ty, maybe_inst);
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}
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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}
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fn shiftNormal(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// Generate a shl_exact/shr_exact
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const result: MCValue = switch (tag) {
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.shl => try self.shiftExact(.shl_exact, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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.shr => try self.shiftExact(.shr_exact, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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else => unreachable,
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};
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// Truncate if necessary
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switch (tag) {
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.shr => return result,
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.shl => {
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const result_reg = result.register;
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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},
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else => unreachable,
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}
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} else {
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return self.fail("TODO binary operations on integers > u64/i64", .{});
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}
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},
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else => unreachable,
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}
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}
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fn booleanOp(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Bool => {
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assert((try lhs_bind.resolveToImmediate(self)) == null); // should have been handled by Sema
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assert((try rhs_bind.resolveToImmediate(self)) == null); // should have been handled by Sema
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.bool_and => .and_shifted_register,
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.bool_or => .orr_shifted_register,
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else => unreachable,
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};
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return try self.binOpRegisterNew(mir_tag_register, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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},
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else => unreachable,
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}
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}
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fn ptrArithmetic(
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self: *Self,
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tag: Air.Inst.Tag,
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@ -2441,16 +2445,24 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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.mod => try self.modulo(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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else => blk: {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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.addwrap => try self.wrappingArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.subwrap => try self.wrappingArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.mulwrap => try self.wrappingArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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break :blk try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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.inst = inst,
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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});
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},
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.bit_and => try self.bitwise(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.bit_or => try self.bitwise(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.xor => try self.bitwise(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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|
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.shl_exact => try self.shiftExact(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
|
||||
.shr_exact => try self.shiftExact(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
|
||||
|
||||
.shl => try self.shiftNormal(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
|
||||
.shr => try self.shiftNormal(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
|
||||
|
||||
.bool_and => try self.booleanOp(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
|
||||
.bool_or => try self.booleanOp(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
|
||||
|
||||
else => unreachable,
|
||||
};
|
||||
};
|
||||
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
|
||||
|
||||
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Reference in New Issue
Block a user