From da8b7fb0c01f3b71af99eee6fcff6b1a9d216f13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Fri, 23 Aug 2024 02:04:59 +0200 Subject: [PATCH] std.Target: Update CPU models/features for LLVM 19. --- lib/std/Target/aarch64.zig | 1160 ++++++++++++++++++++++------------ lib/std/Target/amdgpu.zig | 355 ++++++++++- lib/std/Target/arm.zig | 162 ++--- lib/std/Target/loongarch.zig | 24 +- lib/std/Target/mips.zig | 6 + lib/std/Target/nvptx.zig | 18 + lib/std/Target/powerpc.zig | 63 +- lib/std/Target/riscv.zig | 882 +++++++++++++++++++++++--- lib/std/Target/s390x.zig | 18 + lib/std/Target/wasm.zig | 15 + lib/std/Target/x86.zig | 125 +++- 11 files changed, 2200 insertions(+), 628 deletions(-) diff --git a/lib/std/Target/aarch64.zig b/lib/std/Target/aarch64.zig index b0b895cfeb..800918cc14 100644 --- a/lib/std/Target/aarch64.zig +++ b/lib/std/Target/aarch64.zig @@ -5,15 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - a510, - a520, - a65, - a710, - a720, - a76, - a78, - a78c, - addr_lsl_fast, + addr_lsl_slow_14, aes, aggressive_fma, alternate_sextload_cvt_f32_pattern, @@ -46,7 +38,6 @@ pub const Feature = enum { cmp_bcc_fusion, complxnum, contextidr_el2, - cortex_r82, cpa, crc, crypto, @@ -77,7 +68,7 @@ pub const Feature = enum { fp8dot4, fp8fma, fp_armv8, - fpmr, + fpac, fptoint, fullfp16, fuse_address, @@ -131,6 +122,7 @@ pub const Feature = enum { rcpc3, rcpc_immo, rdm, + reserve_lr_for_ra, reserve_x1, reserve_x10, reserve_x11, @@ -150,7 +142,6 @@ pub const Feature = enum { reserve_x27, reserve_x28, reserve_x3, - reserve_x30, reserve_x4, reserve_x5, reserve_x6, @@ -168,6 +159,7 @@ pub const Feature = enum { sme, sme2, sme2p1, + sme_b16b16, sme_f16f16, sme_f64f64, sme_f8f16, @@ -193,6 +185,7 @@ pub const Feature = enum { sve2_sha3, sve2_sm4, sve2p1, + sve_b16b16, tagged_globals, the, tlb_rmi, @@ -206,6 +199,7 @@ pub const Feature = enum { trbe, uaops, use_experimental_zeroing_pseudos, + use_fixed_over_scalable_if_equal_cost, use_postra_scheduler, use_reciprocal_square_root, use_scalar_inc_vl, @@ -245,112 +239,14 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".fields.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@intFromEnum(Feature.a510)] = .{ - .llvm_name = "a510", - .description = "Cortex-A510 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .fuse_adrp_add, - .fuse_aes, - .use_postra_scheduler, - }), - }; - result[@intFromEnum(Feature.a520)] = .{ - .llvm_name = "a520", - .description = "Cortex-A520 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .fuse_adrp_add, - .fuse_aes, - .use_postra_scheduler, - }), - }; - result[@intFromEnum(Feature.a65)] = .{ - .llvm_name = "a65", - .description = "Cortex-A65 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .enable_select_opt, - .fuse_address, - .fuse_adrp_add, - .fuse_aes, - .fuse_literals, - .predictable_select_expensive, - }), - }; - result[@intFromEnum(Feature.a710)] = .{ - .llvm_name = "a710", - .description = "Cortex-A710 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .addr_lsl_fast, - .alu_lsl_fast, - .cmp_bcc_fusion, - .enable_select_opt, - .fuse_adrp_add, - .fuse_aes, - .predictable_select_expensive, - .use_postra_scheduler, - }), - }; - result[@intFromEnum(Feature.a720)] = .{ - .llvm_name = "a720", - .description = "Cortex-A720 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .addr_lsl_fast, - .alu_lsl_fast, - .cmp_bcc_fusion, - .enable_select_opt, - .fuse_adrp_add, - .fuse_aes, - .predictable_select_expensive, - .use_postra_scheduler, - }), - }; - result[@intFromEnum(Feature.a76)] = .{ - .llvm_name = "a76", - .description = "Cortex-A76 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .addr_lsl_fast, - .alu_lsl_fast, - .enable_select_opt, - .fuse_adrp_add, - .fuse_aes, - .predictable_select_expensive, - }), - }; - result[@intFromEnum(Feature.a78)] = .{ - .llvm_name = "a78", - .description = "Cortex-A78 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .addr_lsl_fast, - .alu_lsl_fast, - .cmp_bcc_fusion, - .enable_select_opt, - .fuse_adrp_add, - .fuse_aes, - .predictable_select_expensive, - .use_postra_scheduler, - }), - }; - result[@intFromEnum(Feature.a78c)] = .{ - .llvm_name = "a78c", - .description = "Cortex-A78C ARM processors", - .dependencies = featureSet(&[_]Feature{ - .addr_lsl_fast, - .alu_lsl_fast, - .cmp_bcc_fusion, - .enable_select_opt, - .fuse_adrp_add, - .fuse_aes, - .predictable_select_expensive, - .use_postra_scheduler, - }), - }; - result[@intFromEnum(Feature.addr_lsl_fast)] = .{ - .llvm_name = "addr-lsl-fast", - .description = "Address operands with logical shift of up to 3 places are cheap", + result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{ + .llvm_name = "addr-lsl-slow-14", + .description = "Address operands with shift amount of 1 or 4 are slow", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.aes)] = .{ .llvm_name = "aes", - .description = "Enable AES support (FEAT_AES, FEAT_PMULL)", + .description = "Enable AES support", .dependencies = featureSet(&[_]Feature{ .neon, }), @@ -367,7 +263,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.altnzcv)] = .{ .llvm_name = "altnzcv", - .description = "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)", + .description = "Enable alternative NZCV format for floating point comparisons", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.alu_lsl_fast)] = .{ @@ -377,12 +273,12 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.am)] = .{ .llvm_name = "am", - .description = "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)", + .description = "Enable Armv8.4-A Activity Monitors extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.amvs)] = .{ .llvm_name = "amvs", - .description = "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", + .description = "Enable Armv8.6-A Activity Monitors Virtualization support", .dependencies = featureSet(&[_]Feature{ .am, }), @@ -404,7 +300,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.b16b16)] = .{ .llvm_name = "b16b16", - .description = "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", + .description = "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions", .dependencies = featureSet(&[_]Feature{ .bf16, }), @@ -416,17 +312,17 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.bf16)] = .{ .llvm_name = "bf16", - .description = "Enable BFloat16 Extension (FEAT_BF16)", + .description = "Enable BFloat16 Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.brbe)] = .{ .llvm_name = "brbe", - .description = "Enable Branch Record Buffer Extension (FEAT_BRBE)", + .description = "Enable Branch Record Buffer Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.bti)] = .{ .llvm_name = "bti", - .description = "Enable Branch Target Identification (FEAT_BTI)", + .description = "Enable Branch Target Identification", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.call_saved_x10)] = .{ @@ -476,27 +372,27 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.ccdp)] = .{ .llvm_name = "ccdp", - .description = "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)", + .description = "Enable Armv8.5-A Cache Clean to Point of Deep Persistence", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ccidx)] = .{ .llvm_name = "ccidx", - .description = "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)", + .description = "Enable Armv8.3-A Extend of the CCSIDR number of sets", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ccpp)] = .{ .llvm_name = "ccpp", - .description = "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)", + .description = "Enable Armv8.2-A data Cache Clean to Point of Persistence", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.chk)] = .{ .llvm_name = "chk", - .description = "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)", + .description = "Enable Armv8.0-A Check Feature Status Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.clrbhb)] = .{ .llvm_name = "clrbhb", - .description = "Enable Clear BHB instruction (FEAT_CLRBHB)", + .description = "Enable Clear BHB instruction", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.cmp_bcc_fusion)] = .{ @@ -506,7 +402,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.complxnum)] = .{ .llvm_name = "complxnum", - .description = "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", + .description = "Enable Armv8.3-A Floating-point complex number support", .dependencies = featureSet(&[_]Feature{ .neon, }), @@ -516,21 +412,14 @@ pub const all_features = blk: { .description = "Enable RW operand Context ID Register (EL2)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.cortex_r82)] = .{ - .llvm_name = "cortex-r82", - .description = "Cortex-R82 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .use_postra_scheduler, - }), - }; result[@intFromEnum(Feature.cpa)] = .{ .llvm_name = "cpa", - .description = "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)", + .description = "Enable Armv9.5-A Checked Pointer Arithmetic", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.crc)] = .{ .llvm_name = "crc", - .description = "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", + .description = "Enable Armv8.0-A CRC-32 checksum instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.crypto)] = .{ @@ -543,12 +432,12 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.cssc)] = .{ .llvm_name = "cssc", - .description = "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)", + .description = "Enable Common Short Sequence Compression (CSSC) instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.d128)] = .{ .llvm_name = "d128", - .description = "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", + .description = "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and instructions", .dependencies = featureSet(&[_]Feature{ .lse128, }), @@ -570,17 +459,19 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.dit)] = .{ .llvm_name = "dit", - .description = "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", + .description = "Enable Armv8.4-A Data Independent Timing instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.dotprod)] = .{ .llvm_name = "dotprod", - .description = "Enable dot product support (FEAT_DotProd)", - .dependencies = featureSet(&[_]Feature{}), + .description = "Enable dot product support", + .dependencies = featureSet(&[_]Feature{ + .neon, + }), }; result[@intFromEnum(Feature.ecv)] = .{ .llvm_name = "ecv", - .description = "Enable enhanced counter virtualization extension (FEAT_ECV)", + .description = "Enable enhanced counter virtualization extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.el2vmsa)] = .{ @@ -600,7 +491,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.ete)] = .{ .llvm_name = "ete", - .description = "Enable Embedded Trace Extension (FEAT_ETE)", + .description = "Enable Embedded Trace Extension", .dependencies = featureSet(&[_]Feature{ .trbe, }), @@ -612,26 +503,26 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.f32mm)] = .{ .llvm_name = "f32mm", - .description = "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", + .description = "Enable Matrix Multiply FP32 Extension", .dependencies = featureSet(&[_]Feature{ .sve, }), }; result[@intFromEnum(Feature.f64mm)] = .{ .llvm_name = "f64mm", - .description = "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", + .description = "Enable Matrix Multiply FP64 Extension", .dependencies = featureSet(&[_]Feature{ .sve, }), }; result[@intFromEnum(Feature.faminmax)] = .{ .llvm_name = "faminmax", - .description = "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)", + .description = "Enable FAMIN and FAMAX instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fgt)] = .{ .llvm_name = "fgt", - .description = "Enable fine grained virtualization traps extension (FEAT_FGT)", + .description = "Enable fine grained virtualization traps extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fix_cortex_a53_835769)] = .{ @@ -641,7 +532,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.flagm)] = .{ .llvm_name = "flagm", - .description = "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", + .description = "Enable Armv8.4-A Flag Manipulation instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fmv)] = .{ @@ -656,49 +547,59 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.fp16fml)] = .{ .llvm_name = "fp16fml", - .description = "Enable FP16 FML instructions (FEAT_FHM)", + .description = "Enable FP16 FML instructions", .dependencies = featureSet(&[_]Feature{ .fullfp16, }), }; result[@intFromEnum(Feature.fp8)] = .{ .llvm_name = "fp8", - .description = "Enable FP8 instructions (FEAT_FP8)", - .dependencies = featureSet(&[_]Feature{}), + .description = "Enable FP8 instructions", + .dependencies = featureSet(&[_]Feature{ + .bf16, + .faminmax, + .lut, + }), }; result[@intFromEnum(Feature.fp8dot2)] = .{ .llvm_name = "fp8dot2", - .description = "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", - .dependencies = featureSet(&[_]Feature{}), + .description = "Enable FP8 2-way dot instructions", + .dependencies = featureSet(&[_]Feature{ + .fp8dot4, + }), }; result[@intFromEnum(Feature.fp8dot4)] = .{ .llvm_name = "fp8dot4", - .description = "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", - .dependencies = featureSet(&[_]Feature{}), + .description = "Enable FP8 4-way dot instructions", + .dependencies = featureSet(&[_]Feature{ + .fp8fma, + }), }; result[@intFromEnum(Feature.fp8fma)] = .{ .llvm_name = "fp8fma", - .description = "Enable fp8 multiply-add instructions (FEAT_FP8FMA)", - .dependencies = featureSet(&[_]Feature{}), + .description = "Enable Armv9.5-A FP8 multiply-add instructions", + .dependencies = featureSet(&[_]Feature{ + .fp8, + }), }; result[@intFromEnum(Feature.fp_armv8)] = .{ .llvm_name = "fp-armv8", - .description = "Enable ARMv8 FP (FEAT_FP)", + .description = "Enable Armv8.0-A Floating Point Extensions", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.fpmr)] = .{ - .llvm_name = "fpmr", - .description = "Enable FPMR Register (FEAT_FPMR)", + result[@intFromEnum(Feature.fpac)] = .{ + .llvm_name = "fpac", + .description = "Enable v8.3-A Pointer Authentication Faulting enhancement", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fptoint)] = .{ .llvm_name = "fptoint", - .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)", + .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fullfp16)] = .{ .llvm_name = "fullfp16", - .description = "Full FP16 (FEAT_FP16)", + .description = "Enable half-precision floating-point data processing", .dependencies = featureSet(&[_]Feature{ .fp_armv8, }), @@ -767,29 +668,29 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.hbc)] = .{ .llvm_name = "hbc", - .description = "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)", + .description = "Enable Armv8.8-A Hinted Conditional Branches Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.hcx)] = .{ .llvm_name = "hcx", - .description = "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)", + .description = "Enable Armv8.7-A HCRX_EL2 system register", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.i8mm)] = .{ .llvm_name = "i8mm", - .description = "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", + .description = "Enable Matrix Multiply Int8 Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ite)] = .{ .llvm_name = "ite", - .description = "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", + .description = "Enable Armv9.4-A Instrumentation Extension", .dependencies = featureSet(&[_]Feature{ .ete, }), }; result[@intFromEnum(Feature.jsconv)] = .{ .llvm_name = "jsconv", - .description = "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", + .description = "Enable Armv8.3-A JavaScript FP conversion instructions", .dependencies = featureSet(&[_]Feature{ .fp_armv8, }), @@ -801,34 +702,34 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.lor)] = .{ .llvm_name = "lor", - .description = "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)", + .description = "Enable Armv8.1-A Limited Ordering Regions extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ls64)] = .{ .llvm_name = "ls64", - .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", + .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.lse)] = .{ .llvm_name = "lse", - .description = "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", + .description = "Enable Armv8.1-A Large System Extension (LSE) atomic instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.lse128)] = .{ .llvm_name = "lse128", - .description = "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", + .description = "Enable Armv9.4-A 128-bit Atomic instructions", .dependencies = featureSet(&[_]Feature{ .lse, }), }; result[@intFromEnum(Feature.lse2)] = .{ .llvm_name = "lse2", - .description = "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)", + .description = "Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.lut)] = .{ .llvm_name = "lut", - .description = "Enable Lookup Table instructions (FEAT_LUT)", + .description = "Enable Lookup Table instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.mec)] = .{ @@ -840,29 +741,29 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.mops)] = .{ .llvm_name = "mops", - .description = "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", + .description = "Enable Armv8.8-A memcpy and memset acceleration instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.mpam)] = .{ .llvm_name = "mpam", - .description = "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)", + .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.mte)] = .{ .llvm_name = "mte", - .description = "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", + .description = "Enable Memory Tagging Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.neon)] = .{ .llvm_name = "neon", - .description = "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", + .description = "Enable Advanced SIMD instructions", .dependencies = featureSet(&[_]Feature{ .fp_armv8, }), }; result[@intFromEnum(Feature.nmi)] = .{ .llvm_name = "nmi", - .description = "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)", + .description = "Enable Armv8.8-A Non-maskable Interrupts", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.no_bti_at_return_twice)] = .{ @@ -887,7 +788,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.nv)] = .{ .llvm_name = "nv", - .description = "Enable v8.4-A Nested Virtualization Enhancement (FEAT_NV, FEAT_NV2)", + .description = "Enable Armv8.4-A Nested Virtualization Enchancement", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.outline_atomics)] = .{ @@ -897,29 +798,29 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.pan)] = .{ .llvm_name = "pan", - .description = "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)", + .description = "Enable Armv8.1-A Privileged Access-Never extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.pan_rwv)] = .{ .llvm_name = "pan-rwv", - .description = "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", + .description = "Enable Armv8.2-A PAN s1e1R and s1e1W Variants", .dependencies = featureSet(&[_]Feature{ .pan, }), }; result[@intFromEnum(Feature.pauth)] = .{ .llvm_name = "pauth", - .description = "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)", + .description = "Enable Armv8.3-A Pointer Authentication extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.pauth_lr)] = .{ .llvm_name = "pauth-lr", - .description = "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)", + .description = "Enable Armv9.5-A PAC enhancements", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.perfmon)] = .{ .llvm_name = "perfmon", - .description = "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)", + .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.predictable_select_expensive)] = .{ @@ -929,7 +830,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.predres)] = .{ .llvm_name = "predres", - .description = "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", + .description = "Enable Armv8.5-A execution and data prediction invalidation instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.prfm_slc_target)] = .{ @@ -939,43 +840,50 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.rand)] = .{ .llvm_name = "rand", - .description = "Enable Random Number generation instructions (FEAT_RNG)", + .description = "Enable Random Number generation instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ras)] = .{ .llvm_name = "ras", - .description = "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)", + .description = "Enable Armv8.0-A Reliability, Availability and Serviceability Extensions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.rasv2)] = .{ .llvm_name = "rasv2", - .description = "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", + .description = "Enable Armv8.9-A Reliability, Availability and Serviceability Extensions", .dependencies = featureSet(&[_]Feature{ .ras, }), }; result[@intFromEnum(Feature.rcpc)] = .{ .llvm_name = "rcpc", - .description = "Enable support for RCPC extension (FEAT_LRCPC)", + .description = "Enable support for RCPC extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.rcpc3)] = .{ .llvm_name = "rcpc3", - .description = "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", + .description = "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set", .dependencies = featureSet(&[_]Feature{ .rcpc_immo, }), }; result[@intFromEnum(Feature.rcpc_immo)] = .{ .llvm_name = "rcpc-immo", - .description = "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", + .description = "Enable Armv8.4-A RCPC instructions with Immediate Offsets", .dependencies = featureSet(&[_]Feature{ .rcpc, }), }; result[@intFromEnum(Feature.rdm)] = .{ .llvm_name = "rdm", - .description = "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)", + .description = "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions", + .dependencies = featureSet(&[_]Feature{ + .neon, + }), + }; + result[@intFromEnum(Feature.reserve_lr_for_ra)] = .{ + .llvm_name = "reserve-lr-for-ra", + .description = "Reserve LR for call use only", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.reserve_x1)] = .{ @@ -1073,11 +981,6 @@ pub const all_features = blk: { .description = "Reserve X3, making it unavailable as a GPR", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.reserve_x30)] = .{ - .llvm_name = "reserve-x30", - .description = "Reserve X30, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.reserve_x4)] = .{ .llvm_name = "reserve-x4", .description = "Reserve X4, making it unavailable as a GPR", @@ -1105,29 +1008,29 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.rme)] = .{ .llvm_name = "rme", - .description = "Enable Realm Management Extension (FEAT_RME)", + .description = "Enable Realm Management Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sb)] = .{ .llvm_name = "sb", - .description = "Enable v8.5 Speculation Barrier (FEAT_SB)", + .description = "Enable Armv8.5-A Speculation Barrier", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sel2)] = .{ .llvm_name = "sel2", - .description = "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)", + .description = "Enable Armv8.4-A Secure Exception Level 2 extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sha2)] = .{ .llvm_name = "sha2", - .description = "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", + .description = "Enable SHA1 and SHA256 support", .dependencies = featureSet(&[_]Feature{ .neon, }), }; result[@intFromEnum(Feature.sha3)] = .{ .llvm_name = "sha3", - .description = "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", + .description = "Enable SHA512 and SHA3 support", .dependencies = featureSet(&[_]Feature{ .sha2, }), @@ -1149,14 +1052,14 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sm4)] = .{ .llvm_name = "sm4", - .description = "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", + .description = "Enable SM3 and SM4 support", .dependencies = featureSet(&[_]Feature{ .neon, }), }; result[@intFromEnum(Feature.sme)] = .{ .llvm_name = "sme", - .description = "Enable Scalable Matrix Extension (SME) (FEAT_SME)", + .description = "Enable Scalable Matrix Extension (SME)", .dependencies = featureSet(&[_]Feature{ .bf16, .use_scalar_inc_vl, @@ -1171,34 +1074,43 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sme2p1)] = .{ .llvm_name = "sme2p1", - .description = "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", + .description = "Enable Scalable Matrix Extension 2.1 instructions", .dependencies = featureSet(&[_]Feature{ .sme2, }), }; + result[@intFromEnum(Feature.sme_b16b16)] = .{ + .llvm_name = "sme-b16b16", + .description = "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions", + .dependencies = featureSet(&[_]Feature{ + .b16b16, + .sme2, + }), + }; result[@intFromEnum(Feature.sme_f16f16)] = .{ .llvm_name = "sme-f16f16", - .description = "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", - .dependencies = featureSet(&[_]Feature{}), + .description = "Enable SME non-widening Float16 instructions", + .dependencies = featureSet(&[_]Feature{ + .sme2, + }), }; result[@intFromEnum(Feature.sme_f64f64)] = .{ .llvm_name = "sme-f64f64", - .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", + .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions", .dependencies = featureSet(&[_]Feature{ .sme, }), }; result[@intFromEnum(Feature.sme_f8f16)] = .{ .llvm_name = "sme-f8f16", - .description = "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", + .description = "Enable Scalable Matrix Extension (SME) F8F16 instructions", .dependencies = featureSet(&[_]Feature{ - .fp8, - .sme2, + .sme_f8f32, }), }; result[@intFromEnum(Feature.sme_f8f32)] = .{ .llvm_name = "sme-f8f32", - .description = "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", + .description = "Enable Scalable Matrix Extension (SME) F8F32 instructions", .dependencies = featureSet(&[_]Feature{ .fp8, .sme2, @@ -1206,7 +1118,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sme_fa64)] = .{ .llvm_name = "sme-fa64", - .description = "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", + .description = "Enable the full A64 instruction set in streaming SVE mode", .dependencies = featureSet(&[_]Feature{ .sme, .sve2, @@ -1214,61 +1126,62 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sme_i16i64)] = .{ .llvm_name = "sme-i16i64", - .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", + .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions", .dependencies = featureSet(&[_]Feature{ .sme, }), }; result[@intFromEnum(Feature.sme_lutv2)] = .{ .llvm_name = "sme-lutv2", - .description = "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)", + .description = "Enable Scalable Matrix Extension (SME) LUTv2 instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.spe)] = .{ .llvm_name = "spe", - .description = "Enable Statistical Profiling extension (FEAT_SPE)", + .description = "Enable Statistical Profiling extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.spe_eef)] = .{ .llvm_name = "spe-eef", - .description = "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)", + .description = "Enable extra register in the Statistical Profiling Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.specres2)] = .{ .llvm_name = "specres2", - .description = "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", + .description = "Enable Speculation Restriction Instruction", .dependencies = featureSet(&[_]Feature{ .predres, }), }; result[@intFromEnum(Feature.specrestrict)] = .{ .llvm_name = "specrestrict", - .description = "Enable architectural speculation restriction (FEAT_CSV2_2)", + .description = "Enable architectural speculation restriction", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ssbs)] = .{ .llvm_name = "ssbs", - .description = "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", + .description = "Enable Speculative Store Bypass Safe bit", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ssve_fp8dot2)] = .{ .llvm_name = "ssve-fp8dot2", - .description = "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", + .description = "Enable SVE2 FP8 2-way dot product instructions", .dependencies = featureSet(&[_]Feature{ - .sme2, + .ssve_fp8dot4, }), }; result[@intFromEnum(Feature.ssve_fp8dot4)] = .{ .llvm_name = "ssve-fp8dot4", - .description = "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", + .description = "Enable SVE2 FP8 4-way dot product instructions", .dependencies = featureSet(&[_]Feature{ - .sme2, + .ssve_fp8fma, }), }; result[@intFromEnum(Feature.ssve_fp8fma)] = .{ .llvm_name = "ssve-fp8fma", - .description = "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", + .description = "Enable SVE2 FP8 multiply-add instructions", .dependencies = featureSet(&[_]Feature{ + .fp8, .sme2, }), }; @@ -1289,14 +1202,14 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sve)] = .{ .llvm_name = "sve", - .description = "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", + .description = "Enable Scalable Vector Extension (SVE) instructions", .dependencies = featureSet(&[_]Feature{ .fullfp16, }), }; result[@intFromEnum(Feature.sve2)] = .{ .llvm_name = "sve2", - .description = "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", + .description = "Enable Scalable Vector Extension 2 (SVE2) instructions", .dependencies = featureSet(&[_]Feature{ .sve, .use_scalar_inc_vl, @@ -1304,7 +1217,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sve2_aes)] = .{ .llvm_name = "sve2-aes", - .description = "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", + .description = "Enable AES SVE2 instructions", .dependencies = featureSet(&[_]Feature{ .aes, .sve2, @@ -1312,14 +1225,14 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sve2_bitperm)] = .{ .llvm_name = "sve2-bitperm", - .description = "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", + .description = "Enable bit permutation SVE2 instructions", .dependencies = featureSet(&[_]Feature{ .sve2, }), }; result[@intFromEnum(Feature.sve2_sha3)] = .{ .llvm_name = "sve2-sha3", - .description = "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", + .description = "Enable SHA3 SVE2 instructions", .dependencies = featureSet(&[_]Feature{ .sha3, .sve2, @@ -1327,7 +1240,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.sve2_sm4)] = .{ .llvm_name = "sve2-sm4", - .description = "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", + .description = "Enable SM4 SVE2 instructions", .dependencies = featureSet(&[_]Feature{ .sm4, .sve2, @@ -1340,6 +1253,13 @@ pub const all_features = blk: { .sve2, }), }; + result[@intFromEnum(Feature.sve_b16b16)] = .{ + .llvm_name = "sve-b16b16", + .description = "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions", + .dependencies = featureSet(&[_]Feature{ + .b16b16, + }), + }; result[@intFromEnum(Feature.tagged_globals)] = .{ .llvm_name = "tagged-globals", .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", @@ -1347,22 +1267,22 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.the)] = .{ .llvm_name = "the", - .description = "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)", + .description = "Enable Armv8.9-A Translation Hardening Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.tlb_rmi)] = .{ .llvm_name = "tlb-rmi", - .description = "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)", + .description = "Enable Armv8.4-A TLB Range and Maintenance instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.tlbiw)] = .{ .llvm_name = "tlbiw", - .description = "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)", + .description = "Enable Armv9.5-A TLBI VMALL for Dirty State", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.tme)] = .{ .llvm_name = "tme", - .description = "Enable Transactional Memory Extension (FEAT_TME)", + .description = "Enable Transactional Memory Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.tpidr_el1)] = .{ @@ -1387,17 +1307,17 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.tracev8_4)] = .{ .llvm_name = "tracev8.4", - .description = "Enable v8.4-A Trace extension (FEAT_TRF)", + .description = "Enable Armv8.4-A Trace extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.trbe)] = .{ .llvm_name = "trbe", - .description = "Enable Trace Buffer Extension (FEAT_TRBE)", + .description = "Enable Trace Buffer Extension", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.uaops)] = .{ .llvm_name = "uaops", - .description = "Enable v8.2 UAO PState (FEAT_UAO)", + .description = "Enable Armv8.2-A UAO PState", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.use_experimental_zeroing_pseudos)] = .{ @@ -1405,6 +1325,11 @@ pub const all_features = blk: { .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.use_fixed_over_scalable_if_equal_cost)] = .{ + .llvm_name = "use-fixed-over-scalable-if-equal-cost", + .description = "Prefer fixed width loop vectorization over scalable if the cost-model assigns equal costs", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.use_postra_scheduler)] = .{ .llvm_name = "use-postra-scheduler", .description = "Schedule again after register allocation", @@ -1422,7 +1347,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_1a)] = .{ .llvm_name = "v8.1a", - .description = "Support ARM v8.1a instructions", + .description = "Support ARM v8.1a architecture", .dependencies = featureSet(&[_]Feature{ .crc, .lor, @@ -1435,7 +1360,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_2a)] = .{ .llvm_name = "v8.2a", - .description = "Support ARM v8.2a instructions", + .description = "Support ARM v8.2a architecture", .dependencies = featureSet(&[_]Feature{ .ccpp, .pan_rwv, @@ -1446,9 +1371,8 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_3a)] = .{ .llvm_name = "v8.3a", - .description = "Support ARM v8.3a instructions", + .description = "Support ARM v8.3a architecture", .dependencies = featureSet(&[_]Feature{ - .ccidx, .complxnum, .jsconv, .pauth, @@ -1458,7 +1382,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_4a)] = .{ .llvm_name = "v8.4a", - .description = "Support ARM v8.4a instructions", + .description = "Support ARM v8.4a architecture", .dependencies = featureSet(&[_]Feature{ .am, .dit, @@ -1476,7 +1400,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_5a)] = .{ .llvm_name = "v8.5a", - .description = "Support ARM v8.5a instructions", + .description = "Support ARM v8.5a architecture", .dependencies = featureSet(&[_]Feature{ .altnzcv, .bti, @@ -1485,13 +1409,12 @@ pub const all_features = blk: { .predres, .sb, .specrestrict, - .ssbs, .v8_4a, }), }; result[@intFromEnum(Feature.v8_6a)] = .{ .llvm_name = "v8.6a", - .description = "Support ARM v8.6a instructions", + .description = "Support ARM v8.6a architecture", .dependencies = featureSet(&[_]Feature{ .amvs, .bf16, @@ -1503,7 +1426,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_7a)] = .{ .llvm_name = "v8.7a", - .description = "Support ARM v8.7a instructions", + .description = "Support ARM v8.7a architecture", .dependencies = featureSet(&[_]Feature{ .hcx, .v8_6a, @@ -1513,7 +1436,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_8a)] = .{ .llvm_name = "v8.8a", - .description = "Support ARM v8.8a instructions", + .description = "Support ARM v8.8a architecture", .dependencies = featureSet(&[_]Feature{ .hbc, .mops, @@ -1523,7 +1446,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8_9a)] = .{ .llvm_name = "v8.9a", - .description = "Support ARM v8.9a instructions", + .description = "Support ARM v8.9a architecture", .dependencies = featureSet(&[_]Feature{ .chk, .clrbhb, @@ -1536,7 +1459,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8a)] = .{ .llvm_name = "v8a", - .description = "Support ARM v8.0a instructions", + .description = "Support ARM v8a architecture", .dependencies = featureSet(&[_]Feature{ .el2vmsa, .el3, @@ -1545,23 +1468,18 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v8r)] = .{ .llvm_name = "v8r", - .description = "Support ARM v8r instructions", + .description = "Support ARM v8r architecture", .dependencies = featureSet(&[_]Feature{ - .ccidx, .ccpp, - .complxnum, .contextidr_el2, .crc, .dit, - .dotprod, .flagm, - .jsconv, .lse, .pan_rwv, .pauth, .ras, .rcpc_immo, - .rdm, .sel2, .specrestrict, .tlb_rmi, @@ -1571,7 +1489,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v9_1a)] = .{ .llvm_name = "v9.1a", - .description = "Support ARM v9.1a instructions", + .description = "Support ARM v9.1a architecture", .dependencies = featureSet(&[_]Feature{ .v8_6a, .v9a, @@ -1579,7 +1497,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v9_2a)] = .{ .llvm_name = "v9.2a", - .description = "Support ARM v9.2a instructions", + .description = "Support ARM v9.2a architecture", .dependencies = featureSet(&[_]Feature{ .v8_7a, .v9_1a, @@ -1587,7 +1505,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v9_3a)] = .{ .llvm_name = "v9.3a", - .description = "Support ARM v9.3a instructions", + .description = "Support ARM v9.3a architecture", .dependencies = featureSet(&[_]Feature{ .v8_8a, .v9_2a, @@ -1595,7 +1513,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v9_4a)] = .{ .llvm_name = "v9.4a", - .description = "Support ARM v9.4a instructions", + .description = "Support ARM v9.4a architecture", .dependencies = featureSet(&[_]Feature{ .v8_9a, .v9_3a, @@ -1603,7 +1521,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v9_5a)] = .{ .llvm_name = "v9.5a", - .description = "Support ARM v9.5a instructions", + .description = "Support ARM v9.5a architecture", .dependencies = featureSet(&[_]Feature{ .cpa, .v9_4a, @@ -1611,28 +1529,26 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.v9a)] = .{ .llvm_name = "v9a", - .description = "Support ARM v9a instructions", + .description = "Support ARM v9a architecture", .dependencies = featureSet(&[_]Feature{ - .mec, - .sve2, .v8_5a, }), }; result[@intFromEnum(Feature.vh)] = .{ .llvm_name = "vh", - .description = "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", + .description = "Enable Armv8.1-A Virtual Host extension", .dependencies = featureSet(&[_]Feature{ .contextidr_el2, }), }; result[@intFromEnum(Feature.wfxt)] = .{ .llvm_name = "wfxt", - .description = "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", + .description = "Enable Armv8.7-A WFET and WFIT instruction", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xs)] = .{ .llvm_name = "xs", - .description = "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)", + .description = "Enable Armv8.7-A limited-TLB-maintenance instruction", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.zcm)] = .{ @@ -1670,6 +1586,7 @@ pub const cpu = struct { .name = "a64fx", .llvm_name = "a64fx", .features = featureSet(&[_]Feature{ + .aes, .aggressive_fma, .arith_bcc_fusion, .complxnum, @@ -1686,19 +1603,22 @@ pub const cpu = struct { .name = "ampere1", .llvm_name = "ampere1", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .aes, .aggressive_fma, .alu_lsl_fast, .arith_bcc_fusion, + .ccidx, .cmp_bcc_fusion, + .fullfp16, .fuse_address, + .fuse_adrp_add, .fuse_aes, .fuse_literals, .ldp_aligned_only, .perfmon, .rand, .sha3, + .ssbs, .store_pair_suppress, .stp_aligned_only, .use_postra_scheduler, @@ -1709,13 +1629,16 @@ pub const cpu = struct { .name = "ampere1a", .llvm_name = "ampere1a", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .aes, .aggressive_fma, .alu_lsl_fast, .arith_bcc_fusion, + .ccidx, .cmp_bcc_fusion, + .fullfp16, .fuse_address, + .fuse_addsub_2reg_const1, + .fuse_adrp_add, .fuse_aes, .fuse_literals, .ldp_aligned_only, @@ -1724,6 +1647,7 @@ pub const cpu = struct { .rand, .sha3, .sm4, + .ssbs, .store_pair_suppress, .stp_aligned_only, .use_postra_scheduler, @@ -1734,11 +1658,11 @@ pub const cpu = struct { .name = "ampere1b", .llvm_name = "ampere1b", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .aes, .aggressive_fma, .alu_lsl_fast, .arith_bcc_fusion, + .ccidx, .cmp_bcc_fusion, .cssc, .enable_select_opt, @@ -1754,6 +1678,7 @@ pub const cpu = struct { .rand, .sha3, .sm4, + .ssbs, .store_pair_suppress, .stp_aligned_only, .use_postra_scheduler, @@ -1764,11 +1689,11 @@ pub const cpu = struct { .name = "apple_a10", .llvm_name = "apple-a10", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .crc, - .crypto, .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, @@ -1776,6 +1701,7 @@ pub const cpu = struct { .pan, .perfmon, .rdm, + .sha2, .store_pair_suppress, .v8a, .vh, @@ -1787,15 +1713,16 @@ pub const cpu = struct { .name = "apple_a11", .llvm_name = "apple-a11", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8_2a, .zcm, @@ -1806,15 +1733,16 @@ pub const cpu = struct { .name = "apple_a12", .llvm_name = "apple-a12", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8_3a, .zcm, @@ -1825,10 +1753,10 @@ pub const cpu = struct { .name = "apple_a13", .llvm_name = "apple-a13", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fuse_aes, @@ -1845,18 +1773,17 @@ pub const cpu = struct { .name = "apple_a14", .llvm_name = "apple-a14", .features = featureSet(&[_]Feature{ + .aes, .aggressive_fma, .alternate_sextload_cvt_f32_pattern, .altnzcv, .arith_bcc_fusion, .arith_cbz_fusion, .ccdp, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fptoint, .fuse_address, - .fuse_adrp_add, .fuse_aes, .fuse_arith_logic, .fuse_crypto_eor, @@ -1878,10 +1805,10 @@ pub const cpu = struct { .name = "apple_a15", .llvm_name = "apple-a15", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fuse_address, @@ -1892,6 +1819,7 @@ pub const cpu = struct { .fuse_literals, .perfmon, .sha3, + .ssbs, .store_pair_suppress, .v8_6a, .zcm, @@ -1902,13 +1830,14 @@ pub const cpu = struct { .name = "apple_a16", .llvm_name = "apple-a16", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fuse_address, + .fuse_adrp_add, .fuse_aes, .fuse_arith_logic, .fuse_crypto_eor, @@ -1917,6 +1846,7 @@ pub const cpu = struct { .hcx, .perfmon, .sha3, + .ssbs, .store_pair_suppress, .v8_6a, .zcm, @@ -1927,13 +1857,14 @@ pub const cpu = struct { .name = "apple_a17", .llvm_name = "apple-a17", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fuse_address, + .fuse_adrp_add, .fuse_aes, .fuse_arith_logic, .fuse_crypto_eor, @@ -1942,6 +1873,7 @@ pub const cpu = struct { .hcx, .perfmon, .sha3, + .ssbs, .store_pair_suppress, .v8_6a, .zcm, @@ -1952,14 +1884,15 @@ pub const cpu = struct { .name = "apple_a7", .llvm_name = "apple-a7", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8a, .zcm, @@ -1971,14 +1904,15 @@ pub const cpu = struct { .name = "apple_a8", .llvm_name = "apple-a8", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8a, .zcm, @@ -1990,14 +1924,15 @@ pub const cpu = struct { .name = "apple_a9", .llvm_name = "apple-a9", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8a, .zcm, @@ -2005,47 +1940,21 @@ pub const cpu = struct { .zcz_fp_workaround, }), }; - pub const apple_latest = CpuModel{ - .name = "apple_latest", - .llvm_name = "apple-latest", - .features = featureSet(&[_]Feature{ - .alternate_sextload_cvt_f32_pattern, - .arith_bcc_fusion, - .arith_cbz_fusion, - .crypto, - .disable_latency_sched_heuristic, - .fp16fml, - .fuse_address, - .fuse_aes, - .fuse_arith_logic, - .fuse_crypto_eor, - .fuse_csel, - .fuse_literals, - .hcx, - .perfmon, - .sha3, - .store_pair_suppress, - .v8_6a, - .zcm, - .zcz, - }), - }; pub const apple_m1 = CpuModel{ .name = "apple_m1", .llvm_name = "apple-m1", .features = featureSet(&[_]Feature{ + .aes, .aggressive_fma, .alternate_sextload_cvt_f32_pattern, .altnzcv, .arith_bcc_fusion, .arith_cbz_fusion, .ccdp, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fptoint, .fuse_address, - .fuse_adrp_add, .fuse_aes, .fuse_arith_logic, .fuse_crypto_eor, @@ -2067,10 +1976,10 @@ pub const cpu = struct { .name = "apple_m2", .llvm_name = "apple-m2", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fuse_address, @@ -2081,6 +1990,7 @@ pub const cpu = struct { .fuse_literals, .perfmon, .sha3, + .ssbs, .store_pair_suppress, .v8_6a, .zcm, @@ -2091,13 +2001,14 @@ pub const cpu = struct { .name = "apple_m3", .llvm_name = "apple-m3", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fp16fml, .fuse_address, + .fuse_adrp_add, .fuse_aes, .fuse_arith_logic, .fuse_crypto_eor, @@ -2106,25 +2017,53 @@ pub const cpu = struct { .hcx, .perfmon, .sha3, + .ssbs, .store_pair_suppress, .v8_6a, .zcm, .zcz, }), }; + pub const apple_m4 = CpuModel{ + .name = "apple_m4", + .llvm_name = "apple-m4", + .features = featureSet(&[_]Feature{ + .aes, + .alternate_sextload_cvt_f32_pattern, + .arith_bcc_fusion, + .arith_cbz_fusion, + .disable_latency_sched_heuristic, + .fp16fml, + .fuse_address, + .fuse_aes, + .fuse_arith_logic, + .fuse_crypto_eor, + .fuse_csel, + .fuse_literals, + .perfmon, + .sha3, + .sme2, + .sme_f64f64, + .sme_i16i64, + .v9_2a, + .zcm, + .zcz, + }), + }; pub const apple_s4 = CpuModel{ .name = "apple_s4", .llvm_name = "apple-s4", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8_3a, .zcm, @@ -2135,15 +2074,16 @@ pub const cpu = struct { .name = "apple_s5", .llvm_name = "apple-s5", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8_3a, .zcm, @@ -2154,18 +2094,42 @@ pub const cpu = struct { .name = "carmel", .llvm_name = "carmel", .features = featureSet(&[_]Feature{ - .crypto, + .aes, .fullfp16, + .sha2, .v8_2a, }), }; + pub const cobalt_100 = CpuModel{ + .name = "cobalt_100", + .llvm_name = "cobalt-100", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .bf16, + .ccidx, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .i8mm, + .mte, + .perfmon, + .predictable_select_expensive, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, + .v9a, + }), + }; pub const cortex_a34 = CpuModel{ .name = "cortex_a34", .llvm_name = "cortex-a34", .features = featureSet(&[_]Feature{ + .aes, .crc, - .crypto, .perfmon, + .sha2, .v8a, }), }; @@ -2173,9 +2137,10 @@ pub const cpu = struct { .name = "cortex_a35", .llvm_name = "cortex-a35", .features = featureSet(&[_]Feature{ + .aes, .crc, - .crypto, .perfmon, + .sha2, .v8a, }), }; @@ -2183,14 +2148,18 @@ pub const cpu = struct { .name = "cortex_a510", .llvm_name = "cortex-a510", .features = featureSet(&[_]Feature{ - .a510, .bf16, + .ccidx, .ete, .fp16fml, + .fuse_adrp_add, + .fuse_aes, .i8mm, .mte, .perfmon, + .ssbs, .sve2_bitperm, + .use_postra_scheduler, .v9a, }), }; @@ -2198,12 +2167,33 @@ pub const cpu = struct { .name = "cortex_a520", .llvm_name = "cortex-a520", .features = featureSet(&[_]Feature{ - .a520, + .ccidx, .ete, .fp16fml, + .fuse_adrp_add, + .fuse_aes, .mte, .perfmon, + .ssbs, .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; + pub const cortex_a520ae = CpuModel{ + .name = "cortex_a520ae", + .llvm_name = "cortex-a520ae", + .features = featureSet(&[_]Feature{ + .ccidx, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .mte, + .perfmon, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, .v9_2a, }), }; @@ -2211,12 +2201,13 @@ pub const cpu = struct { .name = "cortex_a53", .llvm_name = "cortex-a53", .features = featureSet(&[_]Feature{ + .aes, .balance_fp_ops, .crc, - .crypto, .fuse_adrp_add, .fuse_aes, .perfmon, + .sha2, .use_postra_scheduler, .v8a, }), @@ -2225,7 +2216,7 @@ pub const cpu = struct { .name = "cortex_a55", .llvm_name = "cortex-a55", .features = featureSet(&[_]Feature{ - .crypto, + .aes, .dotprod, .fullfp16, .fuse_address, @@ -2233,6 +2224,7 @@ pub const cpu = struct { .fuse_aes, .perfmon, .rcpc, + .sha2, .use_postra_scheduler, .v8_2a, }), @@ -2241,15 +2233,17 @@ pub const cpu = struct { .name = "cortex_a57", .llvm_name = "cortex-a57", .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .aes, .balance_fp_ops, .crc, - .crypto, .enable_select_opt, .fuse_adrp_add, .fuse_aes, .fuse_literals, .perfmon, .predictable_select_expensive, + .sha2, .use_postra_scheduler, .v8a, }), @@ -2258,12 +2252,18 @@ pub const cpu = struct { .name = "cortex_a65", .llvm_name = "cortex-a65", .features = featureSet(&[_]Feature{ - .a65, - .crypto, + .aes, .dotprod, + .enable_select_opt, .fullfp16, + .fuse_address, + .fuse_adrp_add, + .fuse_aes, + .fuse_literals, .perfmon, + .predictable_select_expensive, .rcpc, + .sha2, .ssbs, .v8_2a, }), @@ -2272,12 +2272,18 @@ pub const cpu = struct { .name = "cortex_a65ae", .llvm_name = "cortex-a65ae", .features = featureSet(&[_]Feature{ - .a65, - .crypto, + .aes, .dotprod, + .enable_select_opt, .fullfp16, + .fuse_address, + .fuse_adrp_add, + .fuse_aes, + .fuse_literals, .perfmon, + .predictable_select_expensive, .rcpc, + .sha2, .ssbs, .v8_2a, }), @@ -2286,14 +2292,22 @@ pub const cpu = struct { .name = "cortex_a710", .llvm_name = "cortex-a710", .features = featureSet(&[_]Feature{ - .a710, + .alu_lsl_fast, .bf16, + .ccidx, + .cmp_bcc_fusion, + .enable_select_opt, .ete, .fp16fml, + .fuse_adrp_add, + .fuse_aes, .i8mm, .mte, .perfmon, + .predictable_select_expensive, + .ssbs, .sve2_bitperm, + .use_postra_scheduler, .v9a, }), }; @@ -2301,9 +2315,9 @@ pub const cpu = struct { .name = "cortex_a715", .llvm_name = "cortex-a715", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .alu_lsl_fast, .bf16, + .ccidx, .cmp_bcc_fusion, .enable_select_opt, .ete, @@ -2315,6 +2329,7 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .spe, + .ssbs, .sve2_bitperm, .use_postra_scheduler, .v9a, @@ -2324,14 +2339,16 @@ pub const cpu = struct { .name = "cortex_a72", .llvm_name = "cortex-a72", .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .aes, .crc, - .crypto, .enable_select_opt, .fuse_adrp_add, .fuse_aes, .fuse_literals, .perfmon, .predictable_select_expensive, + .sha2, .v8a, }), }; @@ -2339,14 +2356,68 @@ pub const cpu = struct { .name = "cortex_a720", .llvm_name = "cortex-a720", .features = featureSet(&[_]Feature{ - .a720, + .alu_lsl_fast, + .ccidx, + .cmp_bcc_fusion, + .enable_select_opt, .ete, .fp16fml, + .fuse_adrp_add, + .fuse_aes, .mte, .perfmon, + .predictable_select_expensive, .spe, .spe_eef, + .ssbs, .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; + pub const cortex_a720ae = CpuModel{ + .name = "cortex_a720ae", + .llvm_name = "cortex-a720ae", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .ccidx, + .cmp_bcc_fusion, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .mte, + .perfmon, + .predictable_select_expensive, + .spe, + .spe_eef, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; + pub const cortex_a725 = CpuModel{ + .name = "cortex_a725", + .llvm_name = "cortex-a725", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .ccidx, + .cmp_bcc_fusion, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .mte, + .perfmon, + .predictable_select_expensive, + .spe, + .spe_eef, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, .v9_2a, }), }; @@ -2354,13 +2425,15 @@ pub const cpu = struct { .name = "cortex_a73", .llvm_name = "cortex-a73", .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .aes, .crc, - .crypto, .enable_select_opt, .fuse_adrp_add, .fuse_aes, .perfmon, .predictable_select_expensive, + .sha2, .v8a, }), }; @@ -2368,7 +2441,8 @@ pub const cpu = struct { .name = "cortex_a75", .llvm_name = "cortex-a75", .features = featureSet(&[_]Feature{ - .crypto, + .addr_lsl_slow_14, + .aes, .dotprod, .enable_select_opt, .fullfp16, @@ -2377,6 +2451,7 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rcpc, + .sha2, .v8_2a, }), }; @@ -2384,12 +2459,18 @@ pub const cpu = struct { .name = "cortex_a76", .llvm_name = "cortex-a76", .features = featureSet(&[_]Feature{ - .a76, - .crypto, + .addr_lsl_slow_14, + .aes, + .alu_lsl_fast, .dotprod, + .enable_select_opt, .fullfp16, + .fuse_adrp_add, + .fuse_aes, .perfmon, + .predictable_select_expensive, .rcpc, + .sha2, .ssbs, .v8_2a, }), @@ -2398,12 +2479,18 @@ pub const cpu = struct { .name = "cortex_a76ae", .llvm_name = "cortex-a76ae", .features = featureSet(&[_]Feature{ - .a76, - .crypto, + .addr_lsl_slow_14, + .aes, + .alu_lsl_fast, .dotprod, + .enable_select_opt, .fullfp16, + .fuse_adrp_add, + .fuse_aes, .perfmon, + .predictable_select_expensive, .rcpc, + .sha2, .ssbs, .v8_2a, }), @@ -2412,10 +2499,10 @@ pub const cpu = struct { .name = "cortex_a77", .llvm_name = "cortex-a77", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .addr_lsl_slow_14, + .aes, .alu_lsl_fast, .cmp_bcc_fusion, - .crypto, .dotprod, .enable_select_opt, .fullfp16, @@ -2424,6 +2511,7 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rcpc, + .sha2, .ssbs, .v8_2a, }), @@ -2432,55 +2520,10 @@ pub const cpu = struct { .name = "cortex_a78", .llvm_name = "cortex-a78", .features = featureSet(&[_]Feature{ - .a78, - .crypto, - .dotprod, - .fullfp16, - .perfmon, - .rcpc, - .spe, - .ssbs, - .v8_2a, - }), - }; - pub const cortex_a78c = CpuModel{ - .name = "cortex_a78c", - .llvm_name = "cortex-a78c", - .features = featureSet(&[_]Feature{ - .a78c, - .crypto, - .dotprod, - .flagm, - .fullfp16, - .pauth, - .perfmon, - .rcpc, - .spe, - .ssbs, - .v8_2a, - }), - }; - pub const cortex_r82 = CpuModel{ - .name = "cortex_r82", - .llvm_name = "cortex-r82", - .features = featureSet(&[_]Feature{ - .cortex_r82, - .fp16fml, - .perfmon, - .predres, - .sb, - .ssbs, - .v8r, - }), - }; - pub const cortex_x1 = CpuModel{ - .name = "cortex_x1", - .llvm_name = "cortex-x1", - .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .addr_lsl_slow_14, + .aes, .alu_lsl_fast, .cmp_bcc_fusion, - .crypto, .dotprod, .enable_select_opt, .fullfp16, @@ -2489,6 +2532,114 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rcpc, + .sha2, + .spe, + .ssbs, + .use_postra_scheduler, + .v8_2a, + }), + }; + pub const cortex_a78ae = CpuModel{ + .name = "cortex_a78ae", + .llvm_name = "cortex-a78ae", + .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .aes, + .alu_lsl_fast, + .cmp_bcc_fusion, + .dotprod, + .enable_select_opt, + .fullfp16, + .fuse_adrp_add, + .fuse_aes, + .perfmon, + .predictable_select_expensive, + .rcpc, + .sha2, + .spe, + .ssbs, + .use_postra_scheduler, + .v8_2a, + }), + }; + pub const cortex_a78c = CpuModel{ + .name = "cortex_a78c", + .llvm_name = "cortex-a78c", + .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .aes, + .alu_lsl_fast, + .cmp_bcc_fusion, + .dotprod, + .enable_select_opt, + .flagm, + .fullfp16, + .fuse_adrp_add, + .fuse_aes, + .pauth, + .perfmon, + .predictable_select_expensive, + .rcpc, + .sha2, + .spe, + .ssbs, + .use_postra_scheduler, + .v8_2a, + }), + }; + pub const cortex_r82 = CpuModel{ + .name = "cortex_r82", + .llvm_name = "cortex-r82", + .features = featureSet(&[_]Feature{ + .ccdp, + .complxnum, + .dotprod, + .fp16fml, + .jsconv, + .perfmon, + .predres, + .rdm, + .sb, + .ssbs, + .use_postra_scheduler, + .v8r, + }), + }; + pub const cortex_r82ae = CpuModel{ + .name = "cortex_r82ae", + .llvm_name = "cortex-r82ae", + .features = featureSet(&[_]Feature{ + .ccdp, + .complxnum, + .dotprod, + .fp16fml, + .jsconv, + .perfmon, + .predres, + .rdm, + .sb, + .ssbs, + .use_postra_scheduler, + .v8r, + }), + }; + pub const cortex_x1 = CpuModel{ + .name = "cortex_x1", + .llvm_name = "cortex-x1", + .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .aes, + .alu_lsl_fast, + .cmp_bcc_fusion, + .dotprod, + .enable_select_opt, + .fullfp16, + .fuse_adrp_add, + .fuse_aes, + .perfmon, + .predictable_select_expensive, + .rcpc, + .sha2, .spe, .ssbs, .use_postra_scheduler, @@ -2499,10 +2650,10 @@ pub const cpu = struct { .name = "cortex_x1c", .llvm_name = "cortex-x1c", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .addr_lsl_slow_14, + .aes, .alu_lsl_fast, .cmp_bcc_fusion, - .crypto, .dotprod, .enable_select_opt, .flagm, @@ -2514,6 +2665,7 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rcpc_immo, + .sha2, .spe, .ssbs, .use_postra_scheduler, @@ -2524,9 +2676,9 @@ pub const cpu = struct { .name = "cortex_x2", .llvm_name = "cortex-x2", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .alu_lsl_fast, .bf16, + .ccidx, .cmp_bcc_fusion, .enable_select_opt, .ete, @@ -2537,6 +2689,7 @@ pub const cpu = struct { .mte, .perfmon, .predictable_select_expensive, + .ssbs, .sve2_bitperm, .use_postra_scheduler, .v9a, @@ -2546,9 +2699,9 @@ pub const cpu = struct { .name = "cortex_x3", .llvm_name = "cortex-x3", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .alu_lsl_fast, .bf16, + .ccidx, .enable_select_opt, .ete, .fp16fml, @@ -2559,6 +2712,7 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .spe, + .ssbs, .sve2_bitperm, .use_postra_scheduler, .v9a, @@ -2568,8 +2722,8 @@ pub const cpu = struct { .name = "cortex_x4", .llvm_name = "cortex-x4", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .alu_lsl_fast, + .ccidx, .enable_select_opt, .ete, .fp16fml, @@ -2580,6 +2734,29 @@ pub const cpu = struct { .predictable_select_expensive, .spe, .spe_eef, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; + pub const cortex_x925 = CpuModel{ + .name = "cortex_x925", + .llvm_name = "cortex-x925", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .ccidx, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .mte, + .perfmon, + .predictable_select_expensive, + .spe, + .spe_eef, + .ssbs, .sve2_bitperm, .use_postra_scheduler, .v9_2a, @@ -2589,14 +2766,15 @@ pub const cpu = struct { .name = "cyclone", .llvm_name = "cyclone", .features = featureSet(&[_]Feature{ + .aes, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .perfmon, + .sha2, .store_pair_suppress, .v8a, .zcm, @@ -2651,10 +2829,9 @@ pub const cpu = struct { .name = "exynos_m3", .llvm_name = "exynos-m3", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, .crc, - .crypto, .exynos_cheap_as_move, .force_32bit_jump_tables, .fuse_address, @@ -2664,6 +2841,7 @@ pub const cpu = struct { .fuse_literals, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8a, @@ -2673,11 +2851,10 @@ pub const cpu = struct { .name = "exynos_m4", .llvm_name = "exynos-m4", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .dotprod, .exynos_cheap_as_move, .force_32bit_jump_tables, @@ -2689,6 +2866,7 @@ pub const cpu = struct { .fuse_csel, .fuse_literals, .perfmon, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8_2a, @@ -2699,11 +2877,10 @@ pub const cpu = struct { .name = "exynos_m5", .llvm_name = "exynos-m5", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, .arith_bcc_fusion, .arith_cbz_fusion, - .crypto, .dotprod, .exynos_cheap_as_move, .force_32bit_jump_tables, @@ -2715,6 +2892,7 @@ pub const cpu = struct { .fuse_csel, .fuse_literals, .perfmon, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8_2a, @@ -2725,13 +2903,13 @@ pub const cpu = struct { .name = "falkor", .llvm_name = "falkor", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, .crc, - .crypto, .perfmon, .predictable_select_expensive, .rdm, + .sha2, .slow_strqro_store, .store_pair_suppress, .use_postra_scheduler, @@ -2751,16 +2929,42 @@ pub const cpu = struct { .use_postra_scheduler, }), }; + pub const grace = CpuModel{ + .name = "grace", + .llvm_name = "grace", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .bf16, + .ccidx, + .cmp_bcc_fusion, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .i8mm, + .mte, + .perfmon, + .predictable_select_expensive, + .rand, + .spe, + .ssbs, + .sve2_bitperm, + .use_fixed_over_scalable_if_equal_cost, + .use_postra_scheduler, + .v9a, + }), + }; pub const kryo = CpuModel{ .name = "kryo", .llvm_name = "kryo", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, .crc, - .crypto, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8a, @@ -2771,11 +2975,11 @@ pub const cpu = struct { .name = "neoverse_512tvb", .llvm_name = "neoverse-512tvb", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, .bf16, .ccdp, - .crypto, + .ccidx, .enable_select_opt, .fp16fml, .fuse_adrp_add, @@ -2784,6 +2988,8 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rand, + .sha3, + .sm4, .spe, .ssbs, .sve, @@ -2795,13 +3001,14 @@ pub const cpu = struct { .name = "neoverse_e1", .llvm_name = "neoverse-e1", .features = featureSet(&[_]Feature{ - .crypto, + .aes, .dotprod, .fullfp16, .fuse_adrp_add, .fuse_aes, .perfmon, .rcpc, + .sha2, .ssbs, .use_postra_scheduler, .v8_2a, @@ -2811,9 +3018,9 @@ pub const cpu = struct { .name = "neoverse_n1", .llvm_name = "neoverse-n1", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .addr_lsl_slow_14, + .aes, .alu_lsl_fast, - .crypto, .dotprod, .enable_select_opt, .fullfp16, @@ -2822,6 +3029,7 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rcpc, + .sha2, .spe, .ssbs, .use_postra_scheduler, @@ -2832,31 +3040,57 @@ pub const cpu = struct { .name = "neoverse_n2", .llvm_name = "neoverse-n2", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .alu_lsl_fast, .bf16, + .ccidx, .enable_select_opt, .ete, + .fp16fml, .fuse_adrp_add, .fuse_aes, .i8mm, .mte, .perfmon, .predictable_select_expensive, + .ssbs, .sve2_bitperm, .use_postra_scheduler, .v9a, }), }; + pub const neoverse_n3 = CpuModel{ + .name = "neoverse_n3", + .llvm_name = "neoverse-n3", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .ccidx, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .mte, + .perfmon, + .predictable_select_expensive, + .rand, + .spe, + .spe_eef, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; pub const neoverse_v1 = CpuModel{ .name = "neoverse_v1", .llvm_name = "neoverse-v1", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .addr_lsl_slow_14, + .aes, .alu_lsl_fast, .bf16, .ccdp, - .crypto, + .ccidx, .enable_select_opt, .fp16fml, .fuse_adrp_add, @@ -2866,6 +3100,8 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .rand, + .sha3, + .sm4, .spe, .ssbs, .sve, @@ -2877,9 +3113,10 @@ pub const cpu = struct { .name = "neoverse_v2", .llvm_name = "neoverse-v2", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, .alu_lsl_fast, .bf16, + .ccidx, + .cmp_bcc_fusion, .enable_select_opt, .ete, .fp16fml, @@ -2891,20 +3128,97 @@ pub const cpu = struct { .predictable_select_expensive, .rand, .spe, + .ssbs, .sve2_bitperm, + .use_fixed_over_scalable_if_equal_cost, .use_postra_scheduler, .v9a, }), }; + pub const neoverse_v3 = CpuModel{ + .name = "neoverse_v3", + .llvm_name = "neoverse-v3", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .brbe, + .ccidx, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .ls64, + .mte, + .perfmon, + .predictable_select_expensive, + .rand, + .rme, + .spe, + .spe_eef, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; + pub const neoverse_v3ae = CpuModel{ + .name = "neoverse_v3ae", + .llvm_name = "neoverse-v3ae", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .brbe, + .ccidx, + .enable_select_opt, + .ete, + .fp16fml, + .fuse_adrp_add, + .fuse_aes, + .ls64, + .mte, + .perfmon, + .predictable_select_expensive, + .rand, + .rme, + .spe, + .spe_eef, + .ssbs, + .sve2_bitperm, + .use_postra_scheduler, + .v9_2a, + }), + }; + pub const oryon_1 = CpuModel{ + .name = "oryon_1", + .llvm_name = "oryon-1", + .features = featureSet(&[_]Feature{ + .aes, + .ccidx, + .enable_select_opt, + .fp16fml, + .fuse_address, + .fuse_adrp_add, + .fuse_aes, + .fuse_crypto_eor, + .perfmon, + .rand, + .sha3, + .sm4, + .spe, + .ssbs, + .use_postra_scheduler, + .v8_6a, + }), + }; pub const saphira = CpuModel{ .name = "saphira", .llvm_name = "saphira", .features = featureSet(&[_]Feature{ - .addr_lsl_fast, + .aes, .alu_lsl_fast, - .crypto, + .ccidx, .perfmon, .predictable_select_expensive, + .sha2, .spe, .store_pair_suppress, .use_postra_scheduler, @@ -2916,10 +3230,11 @@ pub const cpu = struct { .name = "thunderx", .llvm_name = "thunderx", .features = featureSet(&[_]Feature{ + .aes, .crc, - .crypto, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8a, @@ -2929,10 +3244,11 @@ pub const cpu = struct { .name = "thunderx2t99", .llvm_name = "thunderx2t99", .features = featureSet(&[_]Feature{ + .aes, .aggressive_fma, .arith_bcc_fusion, - .crypto, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8_1a, @@ -2942,12 +3258,14 @@ pub const cpu = struct { .name = "thunderx3t110", .llvm_name = "thunderx3t110", .features = featureSet(&[_]Feature{ + .aes, .aggressive_fma, .arith_bcc_fusion, .balance_fp_ops, - .crypto, + .ccidx, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .strict_align, .use_postra_scheduler, @@ -2958,10 +3276,11 @@ pub const cpu = struct { .name = "thunderxt81", .llvm_name = "thunderxt81", .features = featureSet(&[_]Feature{ + .aes, .crc, - .crypto, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8a, @@ -2971,10 +3290,11 @@ pub const cpu = struct { .name = "thunderxt83", .llvm_name = "thunderxt83", .features = featureSet(&[_]Feature{ + .aes, .crc, - .crypto, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8a, @@ -2984,10 +3304,11 @@ pub const cpu = struct { .name = "thunderxt88", .llvm_name = "thunderxt88", .features = featureSet(&[_]Feature{ + .aes, .crc, - .crypto, .perfmon, .predictable_select_expensive, + .sha2, .store_pair_suppress, .use_postra_scheduler, .v8a, @@ -2997,13 +3318,14 @@ pub const cpu = struct { .name = "tsv110", .llvm_name = "tsv110", .features = featureSet(&[_]Feature{ + .aes, .complxnum, - .crypto, .dotprod, .fp16fml, .fuse_aes, .jsconv, .perfmon, + .sha2, .spe, .store_pair_suppress, .use_postra_scheduler, diff --git a/lib/std/Target/amdgpu.zig b/lib/std/Target/amdgpu.zig index 0cc7eafe89..b6b03a6bce 100644 --- a/lib/std/Target/amdgpu.zig +++ b/lib/std/Target/amdgpu.zig @@ -8,16 +8,23 @@ pub const Feature = enum { @"16_bit_insts", a16, add_no_carry_insts, + agent_scope_fine_grained_remote_memory_atomics, + allocate1_5xvgprs, aperture_regs, architected_flat_scratch, architected_sgprs, atomic_buffer_global_pk_add_f16_insts, atomic_buffer_global_pk_add_f16_no_rtn_insts, + atomic_buffer_pk_add_bf16_inst, atomic_csub_no_rtn_insts, atomic_ds_pk_add_16_insts, atomic_fadd_no_rtn_insts, atomic_fadd_rtn_insts, atomic_flat_pk_add_16_insts, + atomic_fmin_fmax_flat_f32, + atomic_fmin_fmax_flat_f64, + atomic_fmin_fmax_global_f32, + atomic_fmin_fmax_global_f64, atomic_global_pk_add_bf16_inst, auto_waitcnt_before_barrier, back_off_barrier, @@ -27,6 +34,7 @@ pub const Feature = enum { default_component_zero, dl_insts, dot10_insts, + dot11_insts, dot1_insts, dot2_insts, dot3_insts, @@ -47,6 +55,7 @@ pub const Feature = enum { fast_fmaf, flat_address_space, flat_atomic_fadd_f32_inst, + flat_buffer_global_fadd_f64_inst, flat_for_global, flat_global_insts, flat_inst_offsets, @@ -71,7 +80,6 @@ pub const Feature = enum { gfx10_b_encoding, gfx10_insts, gfx11, - gfx11_full_vgprs, gfx11_insts, gfx12, gfx12_insts, @@ -101,9 +109,12 @@ pub const Feature = enum { mad_mac_f32_insts, mad_mix_insts, mai_insts, + max_hard_clause_length_32, + max_hard_clause_length_63, max_private_element_size_16, max_private_element_size_4, max_private_element_size_8, + memory_atomic_fadd_f32_denormal_support, mfma_inline_literal_bug, mimg_r128, movrel, @@ -120,11 +131,15 @@ pub const Feature = enum { packed_tid, partial_nsa_encoding, pk_fmac_f16_inst, + precise_memory, + priv_enabled_trap2_nop_bug, promote_alloca, prt_strict_null, pseudo_scalar_trans, r128_a16, real_true16, + required_export_priority, + requires_cov6, restricted_soffset, s_memrealtime, s_memtime_inst, @@ -201,6 +216,16 @@ pub const all_features = blk: { .description = "Have VALU add/sub instructions without carry out", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.agent_scope_fine_grained_remote_memory_atomics)] = .{ + .llvm_name = "agent-scope-fine-grained-remote-memory-atomics", + .description = "Agent (device) scoped atomic operations, excluding those directly supported by PCIe (i.e. integer atomic add, exchange, and compare-and-swap), are functional for allocations in host or peer device memory.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.allocate1_5xvgprs)] = .{ + .llvm_name = "allocate1_5xvgprs", + .description = "Has 50% more physical VGPRs and 50% larger allocation granule", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.aperture_regs)] = .{ .llvm_name = "aperture-regs", .description = "Has Memory Aperture Base and Size Registers", @@ -230,6 +255,11 @@ pub const all_features = blk: { .flat_global_insts, }), }; + result[@intFromEnum(Feature.atomic_buffer_pk_add_bf16_inst)] = .{ + .llvm_name = "atomic-buffer-pk-add-bf16-inst", + .description = "Has buffer_atomic_pk_add_bf16 instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.atomic_csub_no_rtn_insts)] = .{ .llvm_name = "atomic-csub-no-rtn-insts", .description = "Has buffer_atomic_csub and global_atomic_csub instructions that don't return original value", @@ -259,6 +289,26 @@ pub const all_features = blk: { .description = "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f32)] = .{ + .llvm_name = "atomic-fmin-fmax-flat-f32", + .description = "Has flat memory instructions for atomicrmw fmin/fmax for float", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f64)] = .{ + .llvm_name = "atomic-fmin-fmax-flat-f64", + .description = "Has flat memory instructions for atomicrmw fmin/fmax for double", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.atomic_fmin_fmax_global_f32)] = .{ + .llvm_name = "atomic-fmin-fmax-global-f32", + .description = "Has global/buffer instructions for atomicrmw fmin/fmax for float", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.atomic_fmin_fmax_global_f64)] = .{ + .llvm_name = "atomic-fmin-fmax-global-f64", + .description = "Has global/buffer instructions for atomicrmw fmin/fmax for float", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.atomic_global_pk_add_bf16_inst)] = .{ .llvm_name = "atomic-global-pk-add-bf16-inst", .description = "Has global_atomic_pk_add_bf16 instruction", @@ -306,6 +356,11 @@ pub const all_features = blk: { .description = "Has v_dot2_f32_f16 instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.dot11_insts)] = .{ + .llvm_name = "dot11-insts", + .description = "Has v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8, v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.dot1_insts)] = .{ .llvm_name = "dot1-insts", .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", @@ -406,6 +461,11 @@ pub const all_features = blk: { .description = "Has flat_atomic_add_f32 instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.flat_buffer_global_fadd_f64_inst)] = .{ + .llvm_name = "flat-buffer-global-fadd-f64-inst", + .description = "Has flat, buffer, and global instructions for f64 atomic fadd", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.flat_for_global)] = .{ .llvm_name = "flat-for-global", .description = "Force to generate flat instruction for global", @@ -504,6 +564,10 @@ pub const all_features = blk: { .a16, .add_no_carry_insts, .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .ci_insts, .default_component_zero, .dpp, @@ -527,6 +591,7 @@ pub const all_features = blk: { .int_clamp_insts, .inv_2pi_inline_imm, .localmemorysize65536, + .max_hard_clause_length_63, .mimg_r128, .movrel, .no_data_dep_hazard, @@ -573,6 +638,8 @@ pub const all_features = blk: { .a16, .add_no_carry_insts, .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .ci_insts, .default_component_zero, .dpp, @@ -599,6 +666,7 @@ pub const all_features = blk: { .int_clamp_insts, .inv_2pi_inline_imm, .localmemorysize65536, + .max_hard_clause_length_32, .mimg_r128, .movrel, .no_data_dep_hazard, @@ -613,11 +681,6 @@ pub const all_features = blk: { .vscnt, }), }; - result[@intFromEnum(Feature.gfx11_full_vgprs)] = .{ - .llvm_name = "gfx11-full-vgprs", - .description = "GFX11 with 50% more physical VGPRs and 50% larger allocation granule than GFX10", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.gfx11_insts)] = .{ .llvm_name = "gfx11-insts", .description = "Additional instructions for GFX11+", @@ -630,7 +693,10 @@ pub const all_features = blk: { .@"16_bit_insts", .a16, .add_no_carry_insts, + .agent_scope_fine_grained_remote_memory_atomics, .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .ci_insts, .default_component_broadcast, .dpp, @@ -655,6 +721,7 @@ pub const all_features = blk: { .int_clamp_insts, .inv_2pi_inline_imm, .localmemorysize65536, + .max_hard_clause_length_32, .mimg_r128, .movrel, .no_data_dep_hazard, @@ -844,6 +911,16 @@ pub const all_features = blk: { .description = "Has mAI instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.max_hard_clause_length_32)] = .{ + .llvm_name = "max-hard-clause-length-32", + .description = "Maximum number of instructions in an explicit S_CLAUSE is 32", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.max_hard_clause_length_63)] = .{ + .llvm_name = "max-hard-clause-length-63", + .description = "Maximum number of instructions in an explicit S_CLAUSE is 63", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.max_private_element_size_16)] = .{ .llvm_name = "max-private-element-size-16", .description = "Maximum private access size may be 16", @@ -859,6 +936,11 @@ pub const all_features = blk: { .description = "Maximum private access size may be 8", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.memory_atomic_fadd_f32_denormal_support)] = .{ + .llvm_name = "memory-atomic-fadd-f32-denormal-support", + .description = "global/flat/buffer atomic fadd for float supports denormal handling", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.mfma_inline_literal_bug)] = .{ .llvm_name = "mfma-inline-literal-bug", .description = "MFMA cannot use inline literal as SrcC", @@ -939,6 +1021,16 @@ pub const all_features = blk: { .description = "Has v_pk_fmac_f16 instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.precise_memory)] = .{ + .llvm_name = "precise-memory", + .description = "Enable precise memory mode", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.priv_enabled_trap2_nop_bug)] = .{ + .llvm_name = "priv-enabled-trap2-nop-bug", + .description = "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.promote_alloca)] = .{ .llvm_name = "promote-alloca", .description = "Enable promote alloca pass", @@ -964,6 +1056,16 @@ pub const all_features = blk: { .description = "Use true 16-bit registers", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.required_export_priority)] = .{ + .llvm_name = "required-export-priority", + .description = "Export priority must be explicitly manipulated on GFX11.5", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.requires_cov6)] = .{ + .llvm_name = "requires-cov6", + .description = "Target Requires Code Object V6", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.restricted_soffset)] = .{ .llvm_name = "restricted-soffset", .description = "Has restricted SOffset (immediate not supported).", @@ -1038,6 +1140,10 @@ pub const all_features = blk: { .llvm_name = "sea-islands", .description = "SEA_ISLANDS GPU generation", .dependencies = featureSet(&[_]Feature{ + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .ci_insts, .default_component_zero, .ds_src2_insts, @@ -1087,6 +1193,8 @@ pub const all_features = blk: { .llvm_name = "southern-islands", .description = "SOUTHERN_ISLANDS GPU generation", .dependencies = featureSet(&[_]Feature{ + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .default_component_zero, .ds_src2_insts, .extended_image_insts, @@ -1365,7 +1473,6 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .wavefrontsize32, .xnack_support, }), }; @@ -1402,7 +1509,6 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .wavefrontsize32, .xnack_support, }), }; @@ -1439,7 +1545,6 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .wavefrontsize32, .xnack_support, }), }; @@ -1471,7 +1576,6 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .wavefrontsize32, .xnack_support, }), }; @@ -1494,7 +1598,6 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, }), }; pub const gfx1031 = CpuModel{ @@ -1516,7 +1619,6 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, }), }; pub const gfx1032 = CpuModel{ @@ -1538,7 +1640,6 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, }), }; pub const gfx1033 = CpuModel{ @@ -1560,7 +1661,6 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, }), }; pub const gfx1034 = CpuModel{ @@ -1582,7 +1682,6 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, }), }; pub const gfx1035 = CpuModel{ @@ -1604,7 +1703,6 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, }), }; pub const gfx1036 = CpuModel{ @@ -1626,13 +1724,66 @@ pub const cpu = struct { .ldsbankcount32, .nsa_encoding, .shader_cycles_register, - .wavefrontsize32, + }), + }; + pub const gfx10_1_generic = CpuModel{ + .name = "gfx10_1_generic", + .llvm_name = "gfx10-1-generic", + .features = featureSet(&[_]Feature{ + .back_off_barrier, + .dl_insts, + .ds_src2_insts, + .flat_segment_offset_bug, + .get_wave_id_inst, + .gfx10, + .inst_fwd_prefetch_bug, + .lds_branch_vmem_war_hazard, + .lds_misaligned_bug, + .ldsbankcount32, + .mad_mac_f32_insts, + .negative_unaligned_scratch_offset_bug, + .nsa_clause_bug, + .nsa_encoding, + .nsa_to_vmem_bug, + .offset_3f_bug, + .requires_cov6, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .smem_to_vector_write_hazard, + .vcmpx_exec_war_hazard, + .vcmpx_permlane_hazard, + .vmem_to_scalar_write_hazard, + .xnack_support, + }), + }; + pub const gfx10_3_generic = CpuModel{ + .name = "gfx10_3_generic", + .llvm_name = "gfx10-3-generic", + .features = featureSet(&[_]Feature{ + .back_off_barrier, + .dl_insts, + .dot10_insts, + .dot1_insts, + .dot2_insts, + .dot5_insts, + .dot6_insts, + .dot7_insts, + .gfx10, + .gfx10_3_insts, + .gfx10_a_encoding, + .gfx10_b_encoding, + .ldsbankcount32, + .nsa_encoding, + .requires_cov6, + .shader_cycles_register, }), }; pub const gfx1100 = CpuModel{ .name = "gfx1100", .llvm_name = "gfx1100", .features = featureSet(&[_]Feature{ + .allocate1_5xvgprs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -1644,25 +1795,26 @@ pub const cpu = struct { .dot9_insts, .flat_atomic_fadd_f32_inst, .gfx11, - .gfx11_full_vgprs, .image_insts, .ldsbankcount32, .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, .msaa_load_dst_sel_bug, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .priv_enabled_trap2_nop_bug, .shader_cycles_register, .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, - .wavefrontsize32, }), }; pub const gfx1101 = CpuModel{ .name = "gfx1101", .llvm_name = "gfx1101", .features = featureSet(&[_]Feature{ + .allocate1_5xvgprs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -1674,18 +1826,18 @@ pub const cpu = struct { .dot9_insts, .flat_atomic_fadd_f32_inst, .gfx11, - .gfx11_full_vgprs, .image_insts, .ldsbankcount32, .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, .msaa_load_dst_sel_bug, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .priv_enabled_trap2_nop_bug, .shader_cycles_register, .valu_trans_use_hazard, .vcmpx_permlane_hazard, - .wavefrontsize32, }), }; pub const gfx1102 = CpuModel{ @@ -1706,15 +1858,16 @@ pub const cpu = struct { .image_insts, .ldsbankcount32, .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, .msaa_load_dst_sel_bug, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .priv_enabled_trap2_nop_bug, .shader_cycles_register, .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, - .wavefrontsize32, }), }; pub const gfx1103 = CpuModel{ @@ -1735,14 +1888,15 @@ pub const cpu = struct { .image_insts, .ldsbankcount32, .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, .msaa_load_dst_sel_bug, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .priv_enabled_trap2_nop_bug, .shader_cycles_register, .valu_trans_use_hazard, .vcmpx_permlane_hazard, - .wavefrontsize32, }), }; pub const gfx1150 = CpuModel{ @@ -1763,20 +1917,50 @@ pub const cpu = struct { .gfx11, .image_insts, .ldsbankcount32, - .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .required_export_priority, .salu_float, .shader_cycles_register, .vcmpx_permlane_hazard, .vgpr_singleuse_hint, - .wavefrontsize32, }), }; pub const gfx1151 = CpuModel{ .name = "gfx1151", .llvm_name = "gfx1151", + .features = featureSet(&[_]Feature{ + .allocate1_5xvgprs, + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .dl_insts, + .dot10_insts, + .dot5_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .flat_atomic_fadd_f32_inst, + .gfx11, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .required_export_priority, + .salu_float, + .shader_cycles_register, + .vcmpx_permlane_hazard, + .vgpr_singleuse_hint, + }), + }; + pub const gfx1152 = CpuModel{ + .name = "gfx1152", + .llvm_name = "gfx1152", .features = featureSet(&[_]Feature{ .architected_flat_scratch, .atomic_fadd_no_rtn_insts, @@ -1790,27 +1974,60 @@ pub const cpu = struct { .dpp_src1_sgpr, .flat_atomic_fadd_f32_inst, .gfx11, - .gfx11_full_vgprs, .image_insts, .ldsbankcount32, - .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .required_export_priority, .salu_float, .shader_cycles_register, .vcmpx_permlane_hazard, .vgpr_singleuse_hint, - .wavefrontsize32, + }), + }; + pub const gfx11_generic = CpuModel{ + .name = "gfx11_generic", + .llvm_name = "gfx11-generic", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .dl_insts, + .dot10_insts, + .dot5_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .flat_atomic_fadd_f32_inst, + .gfx11, + .image_insts, + .ldsbankcount32, + .mad_intra_fwd_bug, + .memory_atomic_fadd_f32_denormal_support, + .msaa_load_dst_sel_bug, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .priv_enabled_trap2_nop_bug, + .required_export_priority, + .requires_cov6, + .shader_cycles_register, + .user_sgpr_init16_bug, + .valu_trans_use_hazard, + .vcmpx_permlane_hazard, }), }; pub const gfx1200 = CpuModel{ .name = "gfx1200", .llvm_name = "gfx1200", .features = featureSet(&[_]Feature{ + .allocate1_5xvgprs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, + .atomic_buffer_pk_add_bf16_inst, .atomic_ds_pk_add_16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -1818,6 +2035,7 @@ pub const cpu = struct { .atomic_global_pk_add_bf16_inst, .dl_insts, .dot10_insts, + .dot11_insts, .dot7_insts, .dot8_insts, .dot9_insts, @@ -1828,6 +2046,7 @@ pub const cpu = struct { .gfx12, .image_insts, .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, .nsa_encoding, .packed_tid, .partial_nsa_encoding, @@ -1838,16 +2057,17 @@ pub const cpu = struct { .shader_cycles_hi_lo_registers, .vcmpx_permlane_hazard, .vgpr_singleuse_hint, - .wavefrontsize32, }), }; pub const gfx1201 = CpuModel{ .name = "gfx1201", .llvm_name = "gfx1201", .features = featureSet(&[_]Feature{ + .allocate1_5xvgprs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, + .atomic_buffer_pk_add_bf16_inst, .atomic_ds_pk_add_16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -1855,6 +2075,7 @@ pub const cpu = struct { .atomic_global_pk_add_bf16_inst, .dl_insts, .dot10_insts, + .dot11_insts, .dot7_insts, .dot8_insts, .dot9_insts, @@ -1865,6 +2086,7 @@ pub const cpu = struct { .gfx12, .image_insts, .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, .nsa_encoding, .packed_tid, .partial_nsa_encoding, @@ -1875,7 +2097,47 @@ pub const cpu = struct { .shader_cycles_hi_lo_registers, .vcmpx_permlane_hazard, .vgpr_singleuse_hint, - .wavefrontsize32, + }), + }; + pub const gfx12_generic = CpuModel{ + .name = "gfx12_generic", + .llvm_name = "gfx12-generic", + .features = featureSet(&[_]Feature{ + .allocate1_5xvgprs, + .architected_flat_scratch, + .architected_sgprs, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_buffer_pk_add_bf16_inst, + .atomic_ds_pk_add_16_insts, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_global_pk_add_bf16_inst, + .dl_insts, + .dot10_insts, + .dot11_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .extended_image_insts, + .flat_atomic_fadd_f32_inst, + .fp8_conversion_insts, + .gfx12, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .pseudo_scalar_trans, + .requires_cov6, + .restricted_soffset, + .salu_float, + .scalar_dwordx3_loads, + .shader_cycles_hi_lo_registers, + .vcmpx_permlane_hazard, + .vgpr_singleuse_hint, }), }; pub const gfx600 = CpuModel{ @@ -2124,6 +2386,8 @@ pub const cpu = struct { .atomic_buffer_global_pk_add_f16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, .back_off_barrier, .dl_insts, .dot10_insts, @@ -2135,6 +2399,7 @@ pub const cpu = struct { .dot6_insts, .dot7_insts, .dpp_64bit, + .flat_buffer_global_fadd_f64_inst, .fma_mix_insts, .fmacf64_inst, .full_rate_64_ops, @@ -2170,12 +2435,15 @@ pub const cpu = struct { .name = "gfx940", .llvm_name = "gfx940", .features = featureSet(&[_]Feature{ + .agent_scope_fine_grained_remote_memory_atomics, .architected_flat_scratch, .atomic_buffer_global_pk_add_f16_insts, .atomic_ds_pk_add_16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, .dl_insts, @@ -2189,6 +2457,7 @@ pub const cpu = struct { .dot7_insts, .dpp_64bit, .flat_atomic_fadd_f32_inst, + .flat_buffer_global_fadd_f64_inst, .fma_mix_insts, .fmacf64_inst, .force_store_sc0_sc1, @@ -2201,6 +2470,7 @@ pub const cpu = struct { .kernarg_preload, .ldsbankcount32, .mai_insts, + .memory_atomic_fadd_f32_denormal_support, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, @@ -2211,12 +2481,15 @@ pub const cpu = struct { .name = "gfx941", .llvm_name = "gfx941", .features = featureSet(&[_]Feature{ + .agent_scope_fine_grained_remote_memory_atomics, .architected_flat_scratch, .atomic_buffer_global_pk_add_f16_insts, .atomic_ds_pk_add_16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, .dl_insts, @@ -2230,6 +2503,7 @@ pub const cpu = struct { .dot7_insts, .dpp_64bit, .flat_atomic_fadd_f32_inst, + .flat_buffer_global_fadd_f64_inst, .fma_mix_insts, .fmacf64_inst, .force_store_sc0_sc1, @@ -2242,6 +2516,7 @@ pub const cpu = struct { .kernarg_preload, .ldsbankcount32, .mai_insts, + .memory_atomic_fadd_f32_denormal_support, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, @@ -2252,12 +2527,15 @@ pub const cpu = struct { .name = "gfx942", .llvm_name = "gfx942", .features = featureSet(&[_]Feature{ + .agent_scope_fine_grained_remote_memory_atomics, .architected_flat_scratch, .atomic_buffer_global_pk_add_f16_insts, .atomic_ds_pk_add_16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, .dl_insts, @@ -2271,6 +2549,7 @@ pub const cpu = struct { .dot7_insts, .dpp_64bit, .flat_atomic_fadd_f32_inst, + .flat_buffer_global_fadd_f64_inst, .fma_mix_insts, .fmacf64_inst, .fp8_conversion_insts, @@ -2282,12 +2561,28 @@ pub const cpu = struct { .kernarg_preload, .ldsbankcount32, .mai_insts, + .memory_atomic_fadd_f32_denormal_support, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, .sramecc_support, }), }; + pub const gfx9_generic = CpuModel{ + .name = "gfx9_generic", + .llvm_name = "gfx9-generic", + .features = featureSet(&[_]Feature{ + .ds_src2_insts, + .extended_image_insts, + .gds, + .gfx9, + .image_gather4_d16_bug, + .image_insts, + .ldsbankcount32, + .mad_mac_f32_insts, + .requires_cov6, + }), + }; pub const hainan = CpuModel{ .name = "hainan", .llvm_name = "hainan", diff --git a/lib/std/Target/arm.zig b/lib/std/Target/arm.zig index 7bb2d6b600..aa0e1e4603 100644 --- a/lib/std/Target/arm.zig +++ b/lib/std/Target/arm.zig @@ -7,9 +7,7 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"32bit", @"8msecext", - a76, aapcs_frame_chain, - aapcs_frame_chain_leaf, aclass, acquire_release, aes, @@ -40,7 +38,6 @@ pub const Feature = enum { dsp, execute_only, expand_fp_mlx, - exynos, fix_cmse_cve_2021_35465, fix_cortex_a57_aes_1742098, fp16, @@ -96,7 +93,6 @@ pub const Feature = enum { lob, long_calls, loop_align, - m3, mclass, mp, muxed_units, @@ -120,7 +116,6 @@ pub const Feature = enum { prefer_ishst, prefer_vmovsr, prof_unpr, - r4, ras, rclass, read_tp_tpidrprw, @@ -140,7 +135,6 @@ pub const Feature = enum { soft_float, splat_vfp_neon, strict_align, - swift, thumb2, thumb_mode, trustzone, @@ -228,23 +222,11 @@ pub const all_features = blk: { .description = "Enable support for ARMv8-M Security Extensions", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.a76)] = .{ - .llvm_name = "a76", - .description = "Cortex-A76 ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.aapcs_frame_chain)] = .{ .llvm_name = "aapcs-frame-chain", .description = "Create an AAPCS compliant frame chain", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.aapcs_frame_chain_leaf)] = .{ - .llvm_name = "aapcs-frame-chain-leaf", - .description = "Create an AAPCS compliant frame chain for leaf functions", - .dependencies = featureSet(&[_]Feature{ - .aapcs_frame_chain, - }), - }; result[@intFromEnum(Feature.aclass)] = .{ .llvm_name = "aclass", .description = "Is application profile ('A' series)", @@ -422,32 +404,9 @@ pub const all_features = blk: { .description = "Expand VFP/NEON MLA/MLS instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.exynos)] = .{ - .llvm_name = "exynos", - .description = "Samsung Exynos processors", - .dependencies = featureSet(&[_]Feature{ - .crc, - .crypto, - .expand_fp_mlx, - .fuse_aes, - .fuse_literals, - .hwdiv, - .hwdiv_arm, - .prof_unpr, - .ret_addr_stack, - .slow_fp_brcc, - .slow_vdup32, - .slow_vgetlni32, - .slowfpvfmx, - .slowfpvmlx, - .splat_vfp_neon, - .wide_stride_vfp, - .zcz, - }), - }; result[@intFromEnum(Feature.fix_cmse_cve_2021_35465)] = .{ .llvm_name = "fix-cmse-cve-2021-35465", - .description = "Mitigate against the cve-2021-35465 security vulnerability", + .description = "Mitigate against the cve-2021-35465 security vulnurability", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fix_cortex_a57_aes_1742098)] = .{ @@ -815,11 +774,6 @@ pub const all_features = blk: { .description = "Prefer 32-bit alignment for loops", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.m3)] = .{ - .llvm_name = "m3", - .description = "Cortex-M3 ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.mclass)] = .{ .llvm_name = "mclass", .description = "Is microcontroller profile ('M' series)", @@ -945,11 +899,6 @@ pub const all_features = blk: { .description = "Is profitable to unpredicate", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.r4)] = .{ - .llvm_name = "r4", - .description = "Cortex-R4 ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.ras)] = .{ .llvm_name = "ras", .description = "Enable Reliability, Availability and Serviceability extensions", @@ -1049,11 +998,6 @@ pub const all_features = blk: { .description = "Disallow all unaligned memory access", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.swift)] = .{ - .llvm_name = "swift", - .description = "Swift ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.thumb2)] = .{ .llvm_name = "thumb2", .description = "Enable Thumb2 instructions", @@ -1508,10 +1452,9 @@ pub const all_features = blk: { .db, .dfb, .dsp, - .fp_armv8, + .fp_armv8d16sp, .has_v8, .mp, - .neon, .rclass, .virtualization, }), @@ -2104,7 +2047,6 @@ pub const cpu = struct { .name = "cortex_a76", .llvm_name = "cortex-a76", .features = featureSet(&[_]Feature{ - .a76, .dotprod, .fullfp16, .v8_2a, @@ -2114,7 +2056,6 @@ pub const cpu = struct { .name = "cortex_a76ae", .llvm_name = "cortex-a76ae", .features = featureSet(&[_]Feature{ - .a76, .dotprod, .fullfp16, .v8_2a, @@ -2138,6 +2079,15 @@ pub const cpu = struct { .v8_2a, }), }; + pub const cortex_a78ae = CpuModel{ + .name = "cortex_a78ae", + .llvm_name = "cortex-a78ae", + .features = featureSet(&[_]Feature{ + .dotprod, + .fullfp16, + .v8_2a, + }), + }; pub const cortex_a78c = CpuModel{ .name = "cortex_a78c", .llvm_name = "cortex-a78c", @@ -2219,7 +2169,6 @@ pub const cpu = struct { .llvm_name = "cortex-m3", .features = featureSet(&[_]Feature{ .loop_align, - .m3, .no_branch_predictor, .use_misched, .v7m, @@ -2315,7 +2264,6 @@ pub const cpu = struct { .llvm_name = "cortex-r4", .features = featureSet(&[_]Feature{ .avoid_partial_cpsr, - .r4, .ret_addr_stack, .v7r, }), @@ -2325,7 +2273,6 @@ pub const cpu = struct { .llvm_name = "cortex-r4f", .features = featureSet(&[_]Feature{ .avoid_partial_cpsr, - .r4, .ret_addr_stack, .slow_fp_brcc, .slowfpvfmx, @@ -2352,7 +2299,20 @@ pub const cpu = struct { .name = "cortex_r52", .llvm_name = "cortex-r52", .features = featureSet(&[_]Feature{ + .fp_armv8, .fpao, + .neon, + .use_misched, + .v8r, + }), + }; + pub const cortex_r52plus = CpuModel{ + .name = "cortex_r52plus", + .llvm_name = "cortex-r52plus", + .features = featureSet(&[_]Feature{ + .fp_armv8, + .fpao, + .neon, .use_misched, .v8r, }), @@ -2418,7 +2378,6 @@ pub const cpu = struct { .ret_addr_stack, .slowfpvfmx, .slowfpvmlx, - .swift, .use_misched, .v8a, .zcz, @@ -2435,24 +2394,60 @@ pub const cpu = struct { .name = "exynos_m1", .llvm_name = null, .features = featureSet(&[_]Feature{ - .exynos, + .expand_fp_mlx, + .fuse_aes, + .fuse_literals, + .prof_unpr, + .ret_addr_stack, + .slow_fp_brcc, + .slow_vdup32, + .slow_vgetlni32, + .slowfpvfmx, + .slowfpvmlx, + .splat_vfp_neon, .v8a, + .wide_stride_vfp, + .zcz, }), }; pub const exynos_m2 = CpuModel{ .name = "exynos_m2", .llvm_name = null, .features = featureSet(&[_]Feature{ - .exynos, + .expand_fp_mlx, + .fuse_aes, + .fuse_literals, + .prof_unpr, + .ret_addr_stack, + .slow_fp_brcc, + .slow_vdup32, + .slow_vgetlni32, + .slowfpvfmx, + .slowfpvmlx, + .splat_vfp_neon, .v8a, + .wide_stride_vfp, + .zcz, }), }; pub const exynos_m3 = CpuModel{ .name = "exynos_m3", .llvm_name = "exynos-m3", .features = featureSet(&[_]Feature{ - .exynos, + .expand_fp_mlx, + .fuse_aes, + .fuse_literals, + .prof_unpr, + .ret_addr_stack, + .slow_fp_brcc, + .slow_vdup32, + .slow_vgetlni32, + .slowfpvfmx, + .slowfpvmlx, + .splat_vfp_neon, .v8a, + .wide_stride_vfp, + .zcz, }), }; pub const exynos_m4 = CpuModel{ @@ -2460,9 +2455,21 @@ pub const cpu = struct { .llvm_name = "exynos-m4", .features = featureSet(&[_]Feature{ .dotprod, - .exynos, + .expand_fp_mlx, .fullfp16, + .fuse_aes, + .fuse_literals, + .prof_unpr, + .ret_addr_stack, + .slow_fp_brcc, + .slow_vdup32, + .slow_vgetlni32, + .slowfpvfmx, + .slowfpvmlx, + .splat_vfp_neon, .v8_2a, + .wide_stride_vfp, + .zcz, }), }; pub const exynos_m5 = CpuModel{ @@ -2470,9 +2477,21 @@ pub const cpu = struct { .llvm_name = "exynos-m5", .features = featureSet(&[_]Feature{ .dotprod, - .exynos, + .expand_fp_mlx, .fullfp16, + .fuse_aes, + .fuse_literals, + .prof_unpr, + .ret_addr_stack, + .slow_fp_brcc, + .slow_vdup32, + .slow_vgetlni32, + .slowfpvfmx, + .slowfpvmlx, + .splat_vfp_neon, .v8_2a, + .wide_stride_vfp, + .zcz, }), }; pub const generic = CpuModel{ @@ -2538,6 +2557,7 @@ pub const cpu = struct { .llvm_name = "neoverse-n2", .features = featureSet(&[_]Feature{ .bf16, + .fp16fml, .i8mm, .v9a, }), @@ -2564,7 +2584,6 @@ pub const cpu = struct { .name = "sc300", .llvm_name = "sc300", .features = featureSet(&[_]Feature{ - .m3, .no_branch_predictor, .use_misched, .v7m, @@ -2618,7 +2637,6 @@ pub const cpu = struct { .slow_vgetlni32, .slowfpvfmx, .slowfpvmlx, - .swift, .use_misched, .v7a, .vfp4, diff --git a/lib/std/Target/loongarch.zig b/lib/std/Target/loongarch.zig index c5a905dc11..a6c19d4450 100644 --- a/lib/std/Target/loongarch.zig +++ b/lib/std/Target/loongarch.zig @@ -7,7 +7,6 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"32bit", @"64bit", - auto_vec, d, f, frecipe, @@ -18,6 +17,7 @@ pub const Feature = enum { lbt, lsx, lvz, + prefer_w_inst, relax, ual, }; @@ -41,11 +41,6 @@ pub const all_features = blk: { .description = "LA64 Basic Integer and Privilege Instruction Set", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.auto_vec)] = .{ - .llvm_name = "auto-vec", - .description = "Experimental auto vectorization", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.d)] = .{ .llvm_name = "d", .description = "'D' (Double-Precision Floating-Point)", @@ -102,6 +97,11 @@ pub const all_features = blk: { .description = "'LVZ' (Loongson Virtualization Extension)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.prefer_w_inst)] = .{ + .llvm_name = "prefer-w-inst", + .description = "Prefer instructions with W suffix", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.relax)] = .{ .llvm_name = "relax", .description = "Enable Linker relaxation", @@ -152,6 +152,18 @@ pub const cpu = struct { .ual, }), }; + pub const la664 = CpuModel{ + .name = "la664", + .llvm_name = "la664", + .features = featureSet(&[_]Feature{ + .@"64bit", + .frecipe, + .lasx, + .lbt, + .lvz, + .ual, + }), + }; pub const loongarch64 = CpuModel{ .name = "loongarch64", .llvm_name = "loongarch64", diff --git a/lib/std/Target/mips.zig b/lib/std/Target/mips.zig index 9638cb3907..d37d21d313 100644 --- a/lib/std/Target/mips.zig +++ b/lib/std/Target/mips.zig @@ -51,6 +51,7 @@ pub const Feature = enum { ptr64, single_float, soft_float, + strict_align, sym32, use_indirect_jump_hazard, use_tcc_in_div, @@ -356,6 +357,11 @@ pub const all_features = blk: { .description = "Does not support floating point instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.strict_align)] = .{ + .llvm_name = "strict-align", + .description = "Disable unaligned load store for r6", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.sym32)] = .{ .llvm_name = "sym32", .description = "Symbols are 32 bit on Mips64", diff --git a/lib/std/Target/nvptx.zig b/lib/std/Target/nvptx.zig index bcdf91027b..1005d6e829 100644 --- a/lib/std/Target/nvptx.zig +++ b/lib/std/Target/nvptx.zig @@ -13,6 +13,7 @@ pub const Feature = enum { ptx50, ptx60, ptx61, + ptx62, ptx63, ptx64, ptx65, @@ -29,6 +30,8 @@ pub const Feature = enum { ptx81, ptx82, ptx83, + ptx84, + ptx85, sm_20, sm_21, sm_30, @@ -101,6 +104,11 @@ pub const all_features = blk: { .description = "Use PTX version 61", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.ptx62)] = .{ + .llvm_name = "ptx62", + .description = "Use PTX version 62", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.ptx63)] = .{ .llvm_name = "ptx63", .description = "Use PTX version 63", @@ -181,6 +189,16 @@ pub const all_features = blk: { .description = "Use PTX version 83", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.ptx84)] = .{ + .llvm_name = "ptx84", + .description = "Use PTX version 84", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ptx85)] = .{ + .llvm_name = "ptx85", + .description = "Use PTX version 85", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.sm_20)] = .{ .llvm_name = "sm_20", .description = "Target SM 20", diff --git a/lib/std/Target/powerpc.zig b/lib/std/Target/powerpc.zig index 19c8735bb3..2be1fca0bb 100644 --- a/lib/std/Target/powerpc.zig +++ b/lib/std/Target/powerpc.zig @@ -8,6 +8,8 @@ pub const Feature = enum { @"64bit", @"64bitregs", aix, + aix_shared_lib_tls_model_opt, + aix_small_local_dynamic_tls, aix_small_local_exec_tls, allow_unaligned_fp_access, altivec, @@ -113,6 +115,16 @@ pub const all_features = blk: { .description = "AIX OS", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.aix_shared_lib_tls_model_opt)] = .{ + .llvm_name = "aix-shared-lib-tls-model-opt", + .description = "Tune TLS model at function level in shared library loaded with the main program (for 64-bit AIX only)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.aix_small_local_dynamic_tls)] = .{ + .llvm_name = "aix-small-local-dynamic-tls", + .description = "Produce a faster local-dynamic TLS sequence for this function for 64-bit AIX", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.aix_small_local_exec_tls)] = .{ .llvm_name = "aix-small-local-exec-tls", .description = "Produce a TOC-free local-exec TLS sequence for this function for 64-bit AIX", @@ -538,8 +550,7 @@ pub const all_features = blk: { .llvm_name = "prefix-instrs", .description = "Enable prefixed instructions", .dependencies = featureSet(&[_]Feature{ - .power8_vector, - .power9_altivec, + .isa_v31_instructions, }), }; result[@intFromEnum(Feature.privileged)] = .{ @@ -990,6 +1001,54 @@ pub const cpu = struct { .two_const_nr, }), }; + pub const pwr11 = CpuModel{ + .name = "pwr11", + .llvm_name = "pwr11", + .features = featureSet(&[_]Feature{ + .@"64bit", + .allow_unaligned_fp_access, + .bpermd, + .cmpb, + .crbits, + .crypto, + .direct_move, + .extdiv, + .fast_MFLR, + .fcpsgn, + .fpcvt, + .fprnd, + .fre, + .fres, + .frsqrte, + .frsqrtes, + .fsqrt, + .fuse_add_logical, + .fuse_arith_add, + .fuse_logical, + .fuse_logical_add, + .fuse_sha3, + .fuse_store, + .htm, + .icbt, + .isa_v206_instructions, + .isel, + .ldbrx, + .lfiwax, + .mfocrf, + .mma, + .partword_atomics, + .pcrelative_memops, + .popcntd, + .power10_vector, + .ppc_postra_sched, + .ppc_prera_sched, + .predictable_select_expensive, + .quadword_atomics, + .recipprec, + .stfiwx, + .two_const_nr, + }), + }; pub const pwr3 = CpuModel{ .name = "pwr3", .llvm_name = "pwr3", diff --git a/lib/std/Target/riscv.zig b/lib/std/Target/riscv.zig index 9ee2ea9114..6d212dbf12 100644 --- a/lib/std/Target/riscv.zig +++ b/lib/std/Target/riscv.zig @@ -9,32 +9,43 @@ pub const Feature = enum { @"64bit", a, auipc_addi_fusion, + b, c, conditional_cmv_fusion, d, dlen_factor_2, e, experimental, + experimental_rva23s64, + experimental_rva23u64, + experimental_rvb23s64, + experimental_rvb23u64, + experimental_rvm23u32, + experimental_smmpm, + experimental_smnpm, + experimental_ssnpm, + experimental_sspm, + experimental_ssqosid, + experimental_supm, experimental_zacas, - experimental_zcmop, - experimental_zfbfmin, + experimental_zalasr, experimental_zicfilp, experimental_zicfiss, - experimental_zimop, - experimental_ztso, - experimental_zvfbfmin, - experimental_zvfbfwma, f, - fast_unaligned_access, forced_atomics, + forced_sw_shadow_stack, h, i, ld_add_fusion, lui_addi_fusion, m, no_default_unroll, - no_optimized_zero_stride_load, no_rvc_hints, + no_sink_splat_operands, + no_trailing_seq_cst_fence, + optimized_zero_stride_load, + predictable_select_expensive, + prefer_w_inst, relax, reserve_x1, reserve_x10, @@ -67,18 +78,47 @@ pub const Feature = enum { reserve_x7, reserve_x8, reserve_x9, + rva20s64, + rva20u64, + rva22s64, + rva22u64, + rvi20u32, + rvi20u64, save_restore, - seq_cst_trailing_fence, + shcounterenw, + shgatpa, shifted_zextw_fusion, short_forward_branch_opt, + shtvala, + shvsatpa, + shvstvala, + shvstvecd, smaia, + smcdeleg, + smcsrind, smepmp, + smstateen, ssaia, + ssccfg, + ssccptr, + sscofpmf, + sscounterenw, + sscsrind, + ssstateen, + ssstrict, + sstc, + sstvala, + sstvecd, + ssu64xl, + svade, + svadu, + svbare, svinval, svnapot, svpbmt, tagged_globals, unaligned_scalar_mem, + unaligned_vector_mem, use_postra_scheduler, v, ventana_veyron, @@ -89,11 +129,14 @@ pub const Feature = enum { xcvmac, xcvmem, xcvsimd, + xsfcease, xsfvcp, xsfvfnrclipxfqf, xsfvfwmaccqqq, xsfvqmaccdod, xsfvqmaccqoq, + xsifivecdiscarddlone, + xsifivecflushdlone, xtheadba, xtheadbb, xtheadbs, @@ -106,8 +149,13 @@ pub const Feature = enum { xtheadsync, xtheadvdot, xventanacondops, + xwchc, za128rs, za64rs, + zaamo, + zabha, + zalrsc, + zama16b, zawrs, zba, zbb, @@ -121,12 +169,14 @@ pub const Feature = enum { zcd, zce, zcf, + zcmop, zcmp, zcmt, zdinx, zexth_fusion, zextw_fusion, zfa, + zfbfmin, zfh, zfhmin, zfinx, @@ -147,6 +197,7 @@ pub const Feature = enum { zihintntl, zihintpause, zihpm, + zimop, zk, zkn, zknd, @@ -158,6 +209,7 @@ pub const Feature = enum { zksh, zkt, zmmul, + ztso, zvbb, zvbc, zve32f, @@ -165,6 +217,8 @@ pub const Feature = enum { zve64d, zve64f, zve64x, + zvfbfmin, + zvfbfwma, zvfh, zvfhmin, zvkb, @@ -201,6 +255,7 @@ pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; pub const all_features = blk: { + @setEvalBranchQuota(2000); const len = @typeInfo(Feature).@"enum".fields.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; @@ -224,6 +279,15 @@ pub const all_features = blk: { .description = "Enable AUIPC+ADDI macrofusion", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.b)] = .{ + .llvm_name = "b", + .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)", + .dependencies = featureSet(&[_]Feature{ + .zba, + .zbb, + .zbs, + }), + }; result[@intFromEnum(Feature.c)] = .{ .llvm_name = "c", .description = "'C' (Compressed Instructions)", @@ -256,61 +320,261 @@ pub const all_features = blk: { .description = "Experimental intrinsics", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.experimental_rva23s64)] = .{ + .llvm_name = "experimental-rva23s64", + .description = "RISC-V experimental-rva23s64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .experimental_ssnpm, + .h, + .i, + .m, + .shcounterenw, + .shgatpa, + .shtvala, + .shvsatpa, + .shvstvala, + .shvstvecd, + .ssccptr, + .sscofpmf, + .sscounterenw, + .ssstateen, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .v, + .za64rs, + .zawrs, + .zba, + .zbb, + .zbs, + .zcb, + .zcmop, + .zfa, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, + .zvfhmin, + .zvkt, + }), + }; + result[@intFromEnum(Feature.experimental_rva23u64)] = .{ + .llvm_name = "experimental-rva23u64", + .description = "RISC-V experimental-rva23u64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .i, + .m, + .v, + .za64rs, + .zawrs, + .zba, + .zbb, + .zbs, + .zcb, + .zcmop, + .zfa, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, + .zvfhmin, + .zvkt, + }), + }; + result[@intFromEnum(Feature.experimental_rvb23s64)] = .{ + .llvm_name = "experimental-rvb23s64", + .description = "RISC-V experimental-rvb23s64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .ssccptr, + .sscofpmf, + .sscounterenw, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .za64rs, + .zawrs, + .zba, + .zbb, + .zbs, + .zcb, + .zcmop, + .zfa, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + }), + }; + result[@intFromEnum(Feature.experimental_rvb23u64)] = .{ + .llvm_name = "experimental-rvb23u64", + .description = "RISC-V experimental-rvb23u64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .za64rs, + .zawrs, + .zba, + .zbb, + .zbs, + .zcb, + .zcmop, + .zfa, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + }), + }; + result[@intFromEnum(Feature.experimental_rvm23u32)] = .{ + .llvm_name = "experimental-rvm23u32", + .description = "RISC-V experimental-rvm23u32 profile", + .dependencies = featureSet(&[_]Feature{ + .@"32bit", + .i, + .m, + .zba, + .zbb, + .zbs, + .zce, + .zcmop, + .zicbop, + .zicond, + .zihintntl, + .zihintpause, + .zimop, + }), + }; + result[@intFromEnum(Feature.experimental_smmpm)] = .{ + .llvm_name = "experimental-smmpm", + .description = "'Smmpm' (Machine-level Pointer Masking for M-mode)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_smnpm)] = .{ + .llvm_name = "experimental-smnpm", + .description = "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_ssnpm)] = .{ + .llvm_name = "experimental-ssnpm", + .description = "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_sspm)] = .{ + .llvm_name = "experimental-sspm", + .description = "'Sspm' (Indicates Supervisor-mode Pointer Masking)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_ssqosid)] = .{ + .llvm_name = "experimental-ssqosid", + .description = "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_supm)] = .{ + .llvm_name = "experimental-supm", + .description = "'Supm' (Indicates User-mode Pointer Masking)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.experimental_zacas)] = .{ .llvm_name = "experimental-zacas", .description = "'Zacas' (Atomic Compare-And-Swap Instructions)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.experimental_zcmop)] = .{ - .llvm_name = "experimental-zcmop", - .description = "'Zcmop' (Compressed May-Be-Operations)", - .dependencies = featureSet(&[_]Feature{ - .zca, - }), - }; - result[@intFromEnum(Feature.experimental_zfbfmin)] = .{ - .llvm_name = "experimental-zfbfmin", - .description = "'Zfbfmin' (Scalar BF16 Converts)", - .dependencies = featureSet(&[_]Feature{ - .f, - }), + result[@intFromEnum(Feature.experimental_zalasr)] = .{ + .llvm_name = "experimental-zalasr", + .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)", + .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.experimental_zicfilp)] = .{ .llvm_name = "experimental-zicfilp", .description = "'Zicfilp' (Landing pad)", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .zicsr, + }), }; result[@intFromEnum(Feature.experimental_zicfiss)] = .{ .llvm_name = "experimental-zicfiss", .description = "'Zicfiss' (Shadow stack)", .dependencies = featureSet(&[_]Feature{ - .experimental_zimop, .zicsr, - }), - }; - result[@intFromEnum(Feature.experimental_zimop)] = .{ - .llvm_name = "experimental-zimop", - .description = "'Zimop' (May-Be-Operations)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@intFromEnum(Feature.experimental_ztso)] = .{ - .llvm_name = "experimental-ztso", - .description = "'Ztso' (Memory Model - Total Store Order)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@intFromEnum(Feature.experimental_zvfbfmin)] = .{ - .llvm_name = "experimental-zvfbfmin", - .description = "'Zvbfmin' (Vector BF16 Converts)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@intFromEnum(Feature.experimental_zvfbfwma)] = .{ - .llvm_name = "experimental-zvfbfwma", - .description = "'Zvfbfwma' (Vector BF16 widening mul-add)", - .dependencies = featureSet(&[_]Feature{ - .experimental_zfbfmin, - .experimental_zvfbfmin, + .zimop, }), }; result[@intFromEnum(Feature.f)] = .{ @@ -320,16 +584,16 @@ pub const all_features = blk: { .zicsr, }), }; - result[@intFromEnum(Feature.fast_unaligned_access)] = .{ - .llvm_name = "fast-unaligned-access", - .description = "Has reasonably performant unaligned loads and stores (both scalar and vector)", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.forced_atomics)] = .{ .llvm_name = "forced-atomics", .description = "Assume that lock-free native-width atomics are available", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.forced_sw_shadow_stack)] = .{ + .llvm_name = "forced-sw-shadow-stack", + .description = "Implement shadow stack with software.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.h)] = .{ .llvm_name = "h", .description = "'H' (Hypervisor)", @@ -353,23 +617,45 @@ pub const all_features = blk: { result[@intFromEnum(Feature.m)] = .{ .llvm_name = "m", .description = "'M' (Integer Multiplication and Division)", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .zmmul, + }), }; result[@intFromEnum(Feature.no_default_unroll)] = .{ .llvm_name = "no-default-unroll", .description = "Disable default unroll preference.", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.no_optimized_zero_stride_load)] = .{ - .llvm_name = "no-optimized-zero-stride-load", - .description = "Hasn't optimized (perform fewer memory operations)zero-stride vector load", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.no_rvc_hints)] = .{ .llvm_name = "no-rvc-hints", .description = "Disable RVC Hint Instructions.", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.no_sink_splat_operands)] = .{ + .llvm_name = "no-sink-splat-operands", + .description = "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.no_trailing_seq_cst_fence)] = .{ + .llvm_name = "no-trailing-seq-cst-fence", + .description = "Disable trailing fence for seq-cst store.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.optimized_zero_stride_load)] = .{ + .llvm_name = "optimized-zero-stride-load", + .description = "Optimized (perform fewer memory operations)zero-stride vector load", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.predictable_select_expensive)] = .{ + .llvm_name = "predictable-select-expensive", + .description = "Prefer likely predicted branches over selects", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.prefer_w_inst)] = .{ + .llvm_name = "prefer-w-inst", + .description = "Prefer instructions with W suffix", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.relax)] = .{ .llvm_name = "relax", .description = "Enable Linker relaxation.", @@ -530,14 +816,144 @@ pub const all_features = blk: { .description = "Reserve X9", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.rva20s64)] = .{ + .llvm_name = "rva20s64", + .description = "RISC-V rva20s64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .ssccptr, + .sstvala, + .sstvecd, + .svade, + .svbare, + .za128rs, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zifencei, + }), + }; + result[@intFromEnum(Feature.rva20u64)] = .{ + .llvm_name = "rva20u64", + .description = "RISC-V rva20u64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .za128rs, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + }), + }; + result[@intFromEnum(Feature.rva22s64)] = .{ + .llvm_name = "rva22s64", + .description = "RISC-V rva22s64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .ssccptr, + .sscounterenw, + .sstvala, + .sstvecd, + .svade, + .svbare, + .svinval, + .svpbmt, + .za64rs, + .zba, + .zbb, + .zbs, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zifencei, + .zihintpause, + .zihpm, + .zkt, + }), + }; + result[@intFromEnum(Feature.rva22u64)] = .{ + .llvm_name = "rva22u64", + .description = "RISC-V rva22u64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .za64rs, + .zba, + .zbb, + .zbs, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zihintpause, + .zihpm, + .zkt, + }), + }; + result[@intFromEnum(Feature.rvi20u32)] = .{ + .llvm_name = "rvi20u32", + .description = "RISC-V rvi20u32 profile", + .dependencies = featureSet(&[_]Feature{ + .@"32bit", + .i, + }), + }; + result[@intFromEnum(Feature.rvi20u64)] = .{ + .llvm_name = "rvi20u64", + .description = "RISC-V rvi20u64 profile", + .dependencies = featureSet(&[_]Feature{ + .@"64bit", + .i, + }), + }; result[@intFromEnum(Feature.save_restore)] = .{ .llvm_name = "save-restore", .description = "Enable save/restore.", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.seq_cst_trailing_fence)] = .{ - .llvm_name = "seq-cst-trailing-fence", - .description = "Enable trailing fence for seq-cst store.", + result[@intFromEnum(Feature.shcounterenw)] = .{ + .llvm_name = "shcounterenw", + .description = "'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.shgatpa)] = .{ + .llvm_name = "shgatpa", + .description = "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.shifted_zextw_fusion)] = .{ @@ -550,21 +966,126 @@ pub const all_features = blk: { .description = "Enable short forward branch optimization", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.shtvala)] = .{ + .llvm_name = "shtvala", + .description = "'Shtvala' (htval provides all needed values)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.shvsatpa)] = .{ + .llvm_name = "shvsatpa", + .description = "'Svsatpa' (vsatp supports all modes supported by satp)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.shvstvala)] = .{ + .llvm_name = "shvstvala", + .description = "'Shvstvala' (vstval provides all needed values)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.shvstvecd)] = .{ + .llvm_name = "shvstvecd", + .description = "'Shvstvecd' (vstvec supports Direct mode)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.smaia)] = .{ .llvm_name = "smaia", .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.smcdeleg)] = .{ + .llvm_name = "smcdeleg", + .description = "'Smcdeleg' (Counter Delegation Machine Level)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.smcsrind)] = .{ + .llvm_name = "smcsrind", + .description = "'Smcsrind' (Indirect CSR Access Machine Level)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.smepmp)] = .{ .llvm_name = "smepmp", .description = "'Smepmp' (Enhanced Physical Memory Protection)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.smstateen)] = .{ + .llvm_name = "smstateen", + .description = "'Smstateen' (Machine-mode view of the state-enable extension)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.ssaia)] = .{ .llvm_name = "ssaia", .description = "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.ssccfg)] = .{ + .llvm_name = "ssccfg", + .description = "'Ssccfg' (Counter Configuration Supervisor Level)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ssccptr)] = .{ + .llvm_name = "ssccptr", + .description = "'Ssccptr' (Main memory supports page table reads)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sscofpmf)] = .{ + .llvm_name = "sscofpmf", + .description = "'Sscofpmf' (Count Overflow and Mode-Based Filtering)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sscounterenw)] = .{ + .llvm_name = "sscounterenw", + .description = "'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sscsrind)] = .{ + .llvm_name = "sscsrind", + .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ssstateen)] = .{ + .llvm_name = "ssstateen", + .description = "'Ssstateen' (Supervisor-mode view of the state-enable extension)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ssstrict)] = .{ + .llvm_name = "ssstrict", + .description = "'Ssstrict' (No non-conforming extensions are present)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sstc)] = .{ + .llvm_name = "sstc", + .description = "'Sstc' (Supervisor-mode timer interrupts)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sstvala)] = .{ + .llvm_name = "sstvala", + .description = "'Sstvala' (stval provides all needed values)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sstvecd)] = .{ + .llvm_name = "sstvecd", + .description = "'Sstvecd' (stvec supports Direct mode)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ssu64xl)] = .{ + .llvm_name = "ssu64xl", + .description = "'Ssu64xl' (UXLEN=64 supported)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.svade)] = .{ + .llvm_name = "svade", + .description = "'Svade' (Raise exceptions on improper A/D bits)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.svadu)] = .{ + .llvm_name = "svadu", + .description = "'Svadu' (Hardware A/D updates)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.svbare)] = .{ + .llvm_name = "svbare", + .description = "'Svbare' $(satp mode Bare supported)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.svinval)] = .{ .llvm_name = "svinval", .description = "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)", @@ -590,6 +1111,11 @@ pub const all_features = blk: { .description = "Has reasonably performant unaligned scalar loads and stores", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.unaligned_vector_mem)] = .{ + .llvm_name = "unaligned-vector-mem", + .description = "Has reasonably performant unaligned vector loads and stores", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.use_postra_scheduler)] = .{ .llvm_name = "use-postra-scheduler", .description = "Schedule again after register allocation", @@ -643,6 +1169,11 @@ pub const all_features = blk: { .description = "'XCVsimd' (CORE-V SIMD ALU)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.xsfcease)] = .{ + .llvm_name = "xsfcease", + .description = "'XSfcease' (SiFive sf.cease Instruction)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.xsfvcp)] = .{ .llvm_name = "xsfvcp", .description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)", @@ -661,7 +1192,7 @@ pub const all_features = blk: { .llvm_name = "xsfvfwmaccqqq", .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", .dependencies = featureSet(&[_]Feature{ - .experimental_zvfbfmin, + .zvfbfmin, }), }; result[@intFromEnum(Feature.xsfvqmaccdod)] = .{ @@ -678,61 +1209,69 @@ pub const all_features = blk: { .zve32x, }), }; + result[@intFromEnum(Feature.xsifivecdiscarddlone)] = .{ + .llvm_name = "xsifivecdiscarddlone", + .description = "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xsifivecflushdlone)] = .{ + .llvm_name = "xsifivecflushdlone", + .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.xtheadba)] = .{ .llvm_name = "xtheadba", - .description = "'xtheadba' (T-Head address calculation instructions)", + .description = "'XTHeadBa' (T-Head address calculation instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadbb)] = .{ .llvm_name = "xtheadbb", - .description = "'xtheadbb' (T-Head basic bit-manipulation instructions)", + .description = "'XTHeadBb' (T-Head basic bit-manipulation instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadbs)] = .{ .llvm_name = "xtheadbs", - .description = "'xtheadbs' (T-Head single-bit instructions)", + .description = "'XTHeadBs' (T-Head single-bit instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadcmo)] = .{ .llvm_name = "xtheadcmo", - .description = "'xtheadcmo' (T-Head cache management instructions)", + .description = "'XTHeadCmo' (T-Head cache management instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadcondmov)] = .{ .llvm_name = "xtheadcondmov", - .description = "'xtheadcondmov' (T-Head conditional move instructions)", + .description = "'XTHeadCondMov' (T-Head conditional move instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadfmemidx)] = .{ .llvm_name = "xtheadfmemidx", - .description = "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)", - .dependencies = featureSet(&[_]Feature{ - .f, - }), + .description = "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)", + .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadmac)] = .{ .llvm_name = "xtheadmac", - .description = "'xtheadmac' (T-Head Multiply-Accumulate Instructions)", + .description = "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadmemidx)] = .{ .llvm_name = "xtheadmemidx", - .description = "'xtheadmemidx' (T-Head Indexed Memory Operations)", + .description = "'XTHeadMemIdx' (T-Head Indexed Memory Operations)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadmempair)] = .{ .llvm_name = "xtheadmempair", - .description = "'xtheadmempair' (T-Head two-GPR Memory Operations)", + .description = "'XTHeadMemPair' (T-Head two-GPR Memory Operations)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadsync)] = .{ .llvm_name = "xtheadsync", - .description = "'xtheadsync' (T-Head multicore synchronization instructions)", + .description = "'XTHeadSync' (T-Head multicore synchronization instructions)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.xtheadvdot)] = .{ .llvm_name = "xtheadvdot", - .description = "'xtheadvdot' (T-Head Vector Extensions for Dot)", + .description = "'XTHeadVdot' (T-Head Vector Extensions for Dot)", .dependencies = featureSet(&[_]Feature{ .v, }), @@ -742,6 +1281,11 @@ pub const all_features = blk: { .description = "'XVentanaCondOps' (Ventana Conditional Ops)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.xwchc)] = .{ + .llvm_name = "xwchc", + .description = "'Xwchc' (WCH/QingKe additional compressed opcodes)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.za128rs)] = .{ .llvm_name = "za128rs", .description = "'Za128rs' (Reservation Set Size of at Most 128 Bytes)", @@ -752,6 +1296,26 @@ pub const all_features = blk: { .description = "'Za64rs' (Reservation Set Size of at Most 64 Bytes)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.zaamo)] = .{ + .llvm_name = "zaamo", + .description = "'Zaamo' (Atomic Memory Operations)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.zabha)] = .{ + .llvm_name = "zabha", + .description = "'Zabha' (Byte and Halfword Atomic Memory Operations)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.zalrsc)] = .{ + .llvm_name = "zalrsc", + .description = "'Zalrsc' (Load-Reserved/Store-Conditional)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.zama16b)] = .{ + .llvm_name = "zama16b", + .description = "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.zawrs)] = .{ .llvm_name = "zawrs", .description = "'Zawrs' (Wait on Reservation Set)", @@ -808,6 +1372,7 @@ pub const all_features = blk: { .llvm_name = "zcd", .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", .dependencies = featureSet(&[_]Feature{ + .d, .zca, }), }; @@ -823,6 +1388,14 @@ pub const all_features = blk: { result[@intFromEnum(Feature.zcf)] = .{ .llvm_name = "zcf", .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", + .dependencies = featureSet(&[_]Feature{ + .f, + .zca, + }), + }; + result[@intFromEnum(Feature.zcmop)] = .{ + .llvm_name = "zcmop", + .description = "'Zcmop' (Compressed May-Be-Operations)", .dependencies = featureSet(&[_]Feature{ .zca, }), @@ -866,6 +1439,13 @@ pub const all_features = blk: { .f, }), }; + result[@intFromEnum(Feature.zfbfmin)] = .{ + .llvm_name = "zfbfmin", + .description = "'Zfbfmin' (Scalar BF16 Converts)", + .dependencies = featureSet(&[_]Feature{ + .f, + }), + }; result[@intFromEnum(Feature.zfh)] = .{ .llvm_name = "zfh", .description = "'Zfh' (Half-Precision Floating-Point)", @@ -980,6 +1560,11 @@ pub const all_features = blk: { .zicsr, }), }; + result[@intFromEnum(Feature.zimop)] = .{ + .llvm_name = "zimop", + .description = "'Zimop' (May-Be-Operations)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.zk)] = .{ .llvm_name = "zk", .description = "'Zk' (Standard scalar cryptography extension)", @@ -1052,6 +1637,11 @@ pub const all_features = blk: { .description = "'Zmmul' (Integer Multiplication)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.ztso)] = .{ + .llvm_name = "ztso", + .description = "'Ztso' (Memory Model - Total Store Order)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.zvbb)] = .{ .llvm_name = "zvbb", .description = "'Zvbb' (Vector basic bit-manipulation instructions)", @@ -1104,6 +1694,21 @@ pub const all_features = blk: { .zvl64b, }), }; + result[@intFromEnum(Feature.zvfbfmin)] = .{ + .llvm_name = "zvfbfmin", + .description = "'Zvbfmin' (Vector BF16 Converts)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; + result[@intFromEnum(Feature.zvfbfwma)] = .{ + .llvm_name = "zvfbfwma", + .description = "'Zvfbfwma' (Vector BF16 widening mul-add)", + .dependencies = featureSet(&[_]Feature{ + .zfbfmin, + .zvfbfmin, + }), + }; result[@intFromEnum(Feature.zvfh)] = .{ .llvm_name = "zvfh", .description = "'Zvfh' (Vector Half-Precision Floating-Point)", @@ -1312,6 +1917,7 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, }), }; @@ -1323,6 +1929,7 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, }), }; @@ -1336,6 +1943,7 @@ pub const cpu = struct { .llvm_name = "generic-rv32", .features = featureSet(&[_]Feature{ .@"32bit", + .i, }), }; pub const generic_rv64 = CpuModel{ @@ -1343,6 +1951,7 @@ pub const cpu = struct { .llvm_name = "generic-rv64", .features = featureSet(&[_]Feature{ .@"64bit", + .i, }), }; pub const rocket = CpuModel{ @@ -1355,6 +1964,7 @@ pub const cpu = struct { .llvm_name = "rocket-rv32", .features = featureSet(&[_]Feature{ .@"32bit", + .i, .zicsr, .zifencei, }), @@ -1364,6 +1974,7 @@ pub const cpu = struct { .llvm_name = "rocket-rv64", .features = featureSet(&[_]Feature{ .@"64bit", + .i, .zicsr, .zifencei, }), @@ -1374,6 +1985,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .no_default_unroll, .short_forward_branch_opt, + .use_postra_scheduler, }), }; pub const sifive_e20 = CpuModel{ @@ -1382,6 +1994,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"32bit", .c, + .i, .m, .zicsr, .zifencei, @@ -1394,6 +2007,7 @@ pub const cpu = struct { .@"32bit", .a, .c, + .i, .m, .zicsr, .zifencei, @@ -1407,6 +2021,7 @@ pub const cpu = struct { .a, .c, .f, + .i, .m, .zifencei, }), @@ -1418,6 +2033,7 @@ pub const cpu = struct { .@"32bit", .a, .c, + .i, .m, .zicsr, .zifencei, @@ -1431,6 +2047,7 @@ pub const cpu = struct { .a, .c, .f, + .i, .m, .zifencei, }), @@ -1443,9 +2060,11 @@ pub const cpu = struct { .a, .c, .f, + .i, .m, .no_default_unroll, .short_forward_branch_opt, + .use_postra_scheduler, .zifencei, }), }; @@ -1459,10 +2078,13 @@ pub const cpu = struct { .c, .conditional_cmv_fusion, .d, - .fast_unaligned_access, + .i, .lui_addi_fusion, .m, .no_default_unroll, + .unaligned_scalar_mem, + .unaligned_vector_mem, + .use_postra_scheduler, .za64rs, .zba, .zbb, @@ -1491,10 +2113,14 @@ pub const cpu = struct { .auipc_addi_fusion, .c, .conditional_cmv_fusion, - .fast_unaligned_access, + .i, .lui_addi_fusion, .m, .no_default_unroll, + .no_sink_splat_operands, + .unaligned_scalar_mem, + .unaligned_vector_mem, + .use_postra_scheduler, .v, .za64rs, .zba, @@ -1527,6 +2153,7 @@ pub const cpu = struct { .@"64bit", .a, .c, + .i, .m, .zicsr, .zifencei, @@ -1539,6 +2166,7 @@ pub const cpu = struct { .@"64bit", .a, .c, + .i, .m, .zicsr, .zifencei, @@ -1552,6 +2180,7 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, .zifencei, }), @@ -1564,9 +2193,11 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, .no_default_unroll, .short_forward_branch_opt, + .use_postra_scheduler, .zifencei, .zihintpause, }), @@ -1579,6 +2210,7 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, .zifencei, }), @@ -1591,9 +2223,11 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, .no_default_unroll, .short_forward_branch_opt, + .use_postra_scheduler, .zifencei, }), }; @@ -1605,9 +2239,12 @@ pub const cpu = struct { .a, .c, .dlen_factor_2, + .i, .m, .no_default_unroll, + .optimized_zero_stride_load, .short_forward_branch_opt, + .use_postra_scheduler, .v, .zba, .zbb, @@ -1617,12 +2254,61 @@ pub const cpu = struct { .zvl512b, }), }; + pub const spacemit_x60 = CpuModel{ + .name = "spacemit_x60", + .llvm_name = "spacemit-x60", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .dlen_factor_2, + .i, + .m, + .ssccptr, + .sscofpmf, + .sscounterenw, + .sstc, + .sstvala, + .sstvecd, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .v, + .za64rs, + .zba, + .zbb, + .zbc, + .zbkc, + .zbs, + .zfh, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintpause, + .zihpm, + .zkt, + .zvfh, + .zvkt, + .zvl256b, + }), + }; pub const syntacore_scr1_base = CpuModel{ .name = "syntacore_scr1_base", .llvm_name = "syntacore-scr1-base", .features = featureSet(&[_]Feature{ .@"32bit", .c, + .i, .no_default_unroll, .zicsr, .zifencei, @@ -1634,12 +2320,42 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"32bit", .c, + .i, .m, .no_default_unroll, .zicsr, .zifencei, }), }; + pub const syntacore_scr3_rv32 = CpuModel{ + .name = "syntacore_scr3_rv32", + .llvm_name = "syntacore-scr3-rv32", + .features = featureSet(&[_]Feature{ + .@"32bit", + .c, + .i, + .m, + .no_default_unroll, + .use_postra_scheduler, + .zicsr, + .zifencei, + }), + }; + pub const syntacore_scr3_rv64 = CpuModel{ + .name = "syntacore_scr3_rv64", + .llvm_name = "syntacore-scr3-rv64", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .i, + .m, + .no_default_unroll, + .use_postra_scheduler, + .zicsr, + .zifencei, + }), + }; pub const veyron_v1 = CpuModel{ .name = "veyron_v1", .llvm_name = "veyron-v1", @@ -1649,6 +2365,7 @@ pub const cpu = struct { .auipc_addi_fusion, .c, .d, + .i, .ld_add_fusion, .lui_addi_fusion, .m, @@ -1678,12 +2395,17 @@ pub const cpu = struct { .a, .c, .d, + .i, .m, + .no_default_unroll, + .shifted_zextw_fusion, .svinval, .zba, .zbb, .zbc, .zbs, + .zexth_fusion, + .zextw_fusion, .zicbom, .zicboz, .zifencei, diff --git a/lib/std/Target/s390x.zig b/lib/std/Target/s390x.zig index 2e7dda40f4..0693b98a79 100644 --- a/lib/std/Target/s390x.zig +++ b/lib/std/Target/s390x.zig @@ -40,7 +40,9 @@ pub const Feature = enum { reset_dat_protection, reset_reference_bits_multiple, soft_float, + test_pending_external_interruption, transactional_execution, + unaligned_symbols, vector, vector_enhancements_1, vector_enhancements_2, @@ -233,11 +235,21 @@ pub const all_features = blk: { .description = "Use software emulation for floating point", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.test_pending_external_interruption)] = .{ + .llvm_name = "test-pending-external-interruption", + .description = "Assume that the test-pending-external-interruption facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.transactional_execution)] = .{ .llvm_name = "transactional-execution", .description = "Assume that the transactional-execution facility is installed", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.unaligned_symbols)] = .{ + .llvm_name = "unaligned-symbols", + .description = "Don't apply the ABI minimum alignment to external symbols.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.vector)] = .{ .llvm_name = "vector", .description = "Assume that the vectory facility is installed", @@ -357,6 +369,7 @@ pub const cpu = struct { .population_count, .processor_assist, .reset_reference_bits_multiple, + .test_pending_external_interruption, .transactional_execution, .vector, .vector_enhancements_1, @@ -396,6 +409,7 @@ pub const cpu = struct { .population_count, .processor_assist, .reset_reference_bits_multiple, + .test_pending_external_interruption, .transactional_execution, .vector, .vector_enhancements_1, @@ -441,6 +455,7 @@ pub const cpu = struct { .processor_assist, .reset_dat_protection, .reset_reference_bits_multiple, + .test_pending_external_interruption, .transactional_execution, .vector, .vector_enhancements_1, @@ -538,6 +553,7 @@ pub const cpu = struct { .population_count, .processor_assist, .reset_reference_bits_multiple, + .test_pending_external_interruption, .transactional_execution, .vector, .vector_enhancements_1, @@ -577,6 +593,7 @@ pub const cpu = struct { .population_count, .processor_assist, .reset_reference_bits_multiple, + .test_pending_external_interruption, .transactional_execution, .vector, .vector_enhancements_1, @@ -622,6 +639,7 @@ pub const cpu = struct { .processor_assist, .reset_dat_protection, .reset_reference_bits_multiple, + .test_pending_external_interruption, .transactional_execution, .vector, .vector_enhancements_1, diff --git a/lib/std/Target/wasm.zig b/lib/std/Target/wasm.zig index 172c3ecf79..40725f949a 100644 --- a/lib/std/Target/wasm.zig +++ b/lib/std/Target/wasm.zig @@ -9,6 +9,7 @@ pub const Feature = enum { bulk_memory, exception_handling, extended_const, + half_precision, multimemory, multivalue, mutable_globals, @@ -49,6 +50,11 @@ pub const all_features = blk: { .description = "Enable extended const expressions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.half_precision)] = .{ + .llvm_name = "half-precision", + .description = "Enable half precision instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.multimemory)] = .{ .llvm_name = "multimemory", .description = "Enable multiple memories", @@ -109,8 +115,15 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .atomics, .bulk_memory, + .exception_handling, + .extended_const, + .half_precision, + .multimemory, + .multivalue, .mutable_globals, .nontrapping_fptoint, + .reference_types, + .relaxed_simd, .sign_ext, .simd128, .tail_call, @@ -120,7 +133,9 @@ pub const cpu = struct { .name = "generic", .llvm_name = "generic", .features = featureSet(&[_]Feature{ + .multivalue, .mutable_globals, + .reference_types, .sign_ext, }), }; diff --git a/lib/std/Target/x86.zig b/lib/std/Target/x86.zig index 50d8d48593..5974fbc7d0 100644 --- a/lib/std/Target/x86.zig +++ b/lib/std/Target/x86.zig @@ -45,6 +45,7 @@ pub const Feature = enum { avxvnniint8, bmi, bmi2, + branch_hint, branchfusion, ccmp, cf, @@ -73,8 +74,10 @@ pub const Feature = enum { fast_15bytenop, fast_7bytenop, fast_bextr, + fast_dpwssd, fast_gather, fast_hops, + fast_imm16, fast_lzcnt, fast_movbe, fast_scalar_fsqrt, @@ -96,6 +99,7 @@ pub const Feature = enum { hreset, idivl_to_divb, idivq_to_divl, + inline_asm_use_gpr32, invpcid, kl, lea_sp, @@ -111,6 +115,7 @@ pub const Feature = enum { movdiri, mwaitx, ndd, + nf, no_bypass_delay, no_bypass_delay_blend, no_bypass_delay_mov, @@ -191,6 +196,7 @@ pub const Feature = enum { xsavec, xsaveopt, xsaves, + zu, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -213,14 +219,14 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.@"3dnow")] = .{ - .llvm_name = "3dnow", + .llvm_name = null, .description = "Enable 3DNow! instructions", .dependencies = featureSet(&[_]Feature{ .mmx, }), }; result[@intFromEnum(Feature.@"3dnowa")] = .{ - .llvm_name = "3dnowa", + .llvm_name = null, .description = "Enable 3DNow! Athlon instructions", .dependencies = featureSet(&[_]Feature{ .@"3dnow", @@ -356,7 +362,7 @@ pub const all_features = blk: { }), }; result[@intFromEnum(Feature.avx512er)] = .{ - .llvm_name = "avx512er", + .llvm_name = null, .description = "Enable AVX-512 Exponential and Reciprocal Instructions", .dependencies = featureSet(&[_]Feature{ .avx512f, @@ -388,7 +394,7 @@ pub const all_features = blk: { }), }; result[@intFromEnum(Feature.avx512pf)] = .{ - .llvm_name = "avx512pf", + .llvm_name = null, .description = "Enable AVX-512 PreFetch Instructions", .dependencies = featureSet(&[_]Feature{ .avx512f, @@ -481,6 +487,11 @@ pub const all_features = blk: { .description = "Support BMI2 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.branch_hint)] = .{ + .llvm_name = "branch-hint", + .description = "Target has branch hint feature", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.branchfusion)] = .{ .llvm_name = "branchfusion", .description = "CMP/TEST can be fused with conditional branches", @@ -625,6 +636,11 @@ pub const all_features = blk: { .description = "Indicates that the BEXTR instruction is implemented as a single uop with good throughput", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.fast_dpwssd)] = .{ + .llvm_name = "fast-dpwssd", + .description = "Prefer vpdpwssd instruction over vpmaddwd+vpaddd instruction sequence", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.fast_gather)] = .{ .llvm_name = "fast-gather", .description = "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)", @@ -635,6 +651,11 @@ pub const all_features = blk: { .description = "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.fast_imm16)] = .{ + .llvm_name = "fast-imm16", + .description = "Prefer a i16 instruction with i16 immediate over extension to i32", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.fast_lzcnt)] = .{ .llvm_name = "fast-lzcnt", .description = "LZCNT instructions are as fast as most simple integer ops", @@ -747,6 +768,11 @@ pub const all_features = blk: { .description = "Use 32-bit divide for positive values less than 2^32", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.inline_asm_use_gpr32)] = .{ + .llvm_name = "inline-asm-use-gpr32", + .description = "Enable use of GPR32 in inline assembly for APX", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.invpcid)] = .{ .llvm_name = "invpcid", .description = "Invalidate Process-Context Identifier", @@ -824,6 +850,11 @@ pub const all_features = blk: { .description = "Support non-destructive destination", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.nf)] = .{ + .llvm_name = "nf", + .description = "Support status flags update suppression", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.no_bypass_delay)] = .{ .llvm_name = "no-bypass-delay", .description = "Has no bypass delay when using the 'wrong' domain", @@ -917,7 +948,7 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.prefetchwt1)] = .{ - .llvm_name = "prefetchwt1", + .llvm_name = null, .description = "Prefetch with Intent to Write and T1 Hint", .dependencies = featureSet(&[_]Feature{}), }; @@ -1269,6 +1300,11 @@ pub const all_features = blk: { .xsave, }), }; + result[@intFromEnum(Feature.zu)] = .{ + .llvm_name = "zu", + .description = "Support zero-upper SETcc/IMUL", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; @@ -1357,6 +1393,7 @@ pub const cpu = struct { .cx16, .fast_scalar_shift_masks, .fxsr, + .idivq_to_divl, .lzcnt, .nopl, .popcnt, @@ -1531,6 +1568,7 @@ pub const cpu = struct { .cmov, .cx8, .nopl, + .prfchw, .slow_shld, .slow_unaligned_mem_16, .vzeroupper, @@ -1548,6 +1586,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -1567,6 +1606,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -1584,6 +1624,7 @@ pub const cpu = struct { .cx8, .fxsr, .nopl, + .prfchw, .slow_shld, .slow_unaligned_mem_16, .sse, @@ -1602,6 +1643,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -1619,6 +1661,7 @@ pub const cpu = struct { .cx8, .fxsr, .nopl, + .prfchw, .slow_shld, .slow_unaligned_mem_16, .sse, @@ -1634,6 +1677,7 @@ pub const cpu = struct { .cmov, .cx8, .nopl, + .prfchw, .slow_shld, .slow_unaligned_mem_16, .vzeroupper, @@ -1649,6 +1693,7 @@ pub const cpu = struct { .cx8, .fxsr, .nopl, + .prfchw, .slow_shld, .slow_unaligned_mem_16, .sse, @@ -1663,6 +1708,7 @@ pub const cpu = struct { .@"64bit", .cmov, .cx16, + .fast_imm16, .fxsr, .idivl_to_divb, .idivq_to_divl, @@ -1693,6 +1739,7 @@ pub const cpu = struct { .cx16, .false_deps_popcnt, .fast_7bytenop, + .fast_imm16, .fast_movbe, .fsgsbase, .fxsr, @@ -1731,6 +1778,7 @@ pub const cpu = struct { .cx16, .fast_scalar_shift_masks, .fxsr, + .idivq_to_divl, .lzcnt, .nopl, .popcnt, @@ -1756,6 +1804,7 @@ pub const cpu = struct { .fast_11bytenop, .fast_scalar_shift_masks, .fxsr, + .idivq_to_divl, .lwp, .lzcnt, .mmx, @@ -1790,6 +1839,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fma, .fxsr, + .idivq_to_divl, .lwp, .lzcnt, .mmx, @@ -1826,6 +1876,7 @@ pub const cpu = struct { .fma, .fsgsbase, .fxsr, + .idivq_to_divl, .lwp, .lzcnt, .mmx, @@ -1864,6 +1915,7 @@ pub const cpu = struct { .fma, .fsgsbase, .fxsr, + .idivq_to_divl, .lwp, .lzcnt, .mmx, @@ -1891,6 +1943,7 @@ pub const cpu = struct { .@"64bit", .cmov, .cx16, + .fast_imm16, .fxsr, .idivl_to_divb, .idivq_to_divl, @@ -1963,9 +2016,11 @@ pub const cpu = struct { .cmov, .cx16, .fast_15bytenop, + .fast_imm16, .fast_scalar_shift_masks, .fast_vector_shift_masks, .fxsr, + .idivq_to_divl, .lzcnt, .mmx, .nopl, @@ -1994,11 +2049,13 @@ pub const cpu = struct { .fast_15bytenop, .fast_bextr, .fast_hops, + .fast_imm16, .fast_lzcnt, .fast_movbe, .fast_scalar_shift_masks, .fast_vector_shift_masks, .fxsr, + .idivq_to_divl, .lzcnt, .mmx, .movbe, @@ -2019,6 +2076,7 @@ pub const cpu = struct { .llvm_name = "c3", .features = featureSet(&[_]Feature{ .@"3dnow", + .prfchw, .slow_unaligned_mem_16, .vzeroupper, .x87, @@ -2324,6 +2382,7 @@ pub const cpu = struct { .crc32, .cx16, .fxsr, + .idivq_to_divl, .macrofusion, .mmx, .no_bypass_delay_mov, @@ -2441,6 +2500,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3dnowa", .cx8, + .prfchw, .slow_unaligned_mem_16, .vzeroupper, .x87, @@ -2457,6 +2517,7 @@ pub const cpu = struct { .crc32, .cx16, .false_deps_popcnt, + .fast_imm16, .fast_movbe, .fsgsbase, .fxsr, @@ -2493,6 +2554,7 @@ pub const cpu = struct { .cmov, .crc32, .cx16, + .fast_imm16, .fast_movbe, .fsgsbase, .fxsr, @@ -2547,8 +2609,6 @@ pub const cpu = struct { .fxsr, .gfni, .hreset, - .idivl_to_divb, - .idivq_to_divl, .invpcid, .lzcnt, .macrofusion, @@ -2602,7 +2662,11 @@ pub const cpu = struct { .cx16, .enqcmd, .f16c, - .fast_movbe, + .false_deps_popcnt, + .fast_15bytenop, + .fast_scalar_fsqrt, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, .fma, .fsgsbase, .fxsr, @@ -2610,11 +2674,11 @@ pub const cpu = struct { .hreset, .invpcid, .lzcnt, + .macrofusion, .mmx, .movbe, .movdir64b, .movdiri, - .no_bypass_delay, .nopl, .pconfig, .pku, @@ -2628,11 +2692,8 @@ pub const cpu = struct { .serialize, .sha, .shstk, - .slow_incdec, - .slow_lea, - .slow_two_mem_ops, + .slow_3ops_lea, .uintr, - .use_glm_div_sqrt_costs, .vaes, .vpclmulqdq, .vzeroupper, @@ -2666,6 +2727,7 @@ pub const cpu = struct { .avxvnni, .bmi, .bmi2, + .branch_hint, .cldemote, .clflushopt, .clwb, @@ -2754,6 +2816,7 @@ pub const cpu = struct { .avxvnni, .bmi, .bmi2, + .branch_hint, .cldemote, .clflushopt, .clwb, @@ -3080,6 +3143,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3dnow", .cx8, + .prfchw, .slow_unaligned_mem_16, .vzeroupper, .x87, @@ -3091,6 +3155,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3dnow", .cx8, + .prfchw, .slow_unaligned_mem_16, .vzeroupper, .x87, @@ -3107,6 +3172,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -3126,6 +3192,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -3151,6 +3218,7 @@ pub const cpu = struct { .cx16, .evex512, .fast_gather, + .fast_imm16, .fast_movbe, .fsgsbase, .fxsr, @@ -3193,6 +3261,7 @@ pub const cpu = struct { .cx16, .evex512, .fast_gather, + .fast_imm16, .fast_movbe, .fsgsbase, .fxsr, @@ -3384,6 +3453,7 @@ pub const cpu = struct { .crc32, .cx16, .fxsr, + .idivq_to_divl, .macrofusion, .mmx, .no_bypass_delay_mov, @@ -3422,6 +3492,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -3441,6 +3512,7 @@ pub const cpu = struct { .fast_scalar_shift_masks, .fxsr, .nopl, + .prfchw, .sbb_dep_breaking, .slow_shld, .slow_unaligned_mem_16, @@ -3937,7 +4009,11 @@ pub const cpu = struct { .cx16, .enqcmd, .f16c, - .fast_movbe, + .false_deps_popcnt, + .fast_15bytenop, + .fast_scalar_fsqrt, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, .fma, .fsgsbase, .fxsr, @@ -3945,11 +4021,11 @@ pub const cpu = struct { .hreset, .invpcid, .lzcnt, + .macrofusion, .mmx, .movbe, .movdir64b, .movdiri, - .no_bypass_delay, .nopl, .pconfig, .pku, @@ -3963,11 +4039,8 @@ pub const cpu = struct { .serialize, .sha, .shstk, - .slow_incdec, - .slow_lea, - .slow_two_mem_ops, + .slow_3ops_lea, .uintr, - .use_glm_div_sqrt_costs, .vaes, .vpclmulqdq, .vzeroupper, @@ -3989,6 +4062,7 @@ pub const cpu = struct { .cx16, .false_deps_popcnt, .fast_7bytenop, + .fast_imm16, .fast_movbe, .fxsr, .idivq_to_divl, @@ -4191,6 +4265,7 @@ pub const cpu = struct { .cx16, .false_deps_popcnt, .fast_7bytenop, + .fast_imm16, .fast_movbe, .fxsr, .idivq_to_divl, @@ -4293,6 +4368,7 @@ pub const cpu = struct { .cmov, .crc32, .cx16, + .fast_imm16, .fast_movbe, .fsgsbase, .fxsr, @@ -4331,6 +4407,7 @@ pub const cpu = struct { .crc32, .cx16, .fxsr, + .idivq_to_divl, .macrofusion, .mmx, .no_bypass_delay_mov, @@ -4348,6 +4425,7 @@ pub const cpu = struct { .llvm_name = "winchip2", .features = featureSet(&[_]Feature{ .@"3dnow", + .prfchw, .slow_unaligned_mem_16, .vzeroupper, .x87, @@ -4519,6 +4597,7 @@ pub const cpu = struct { .f16c, .fast_15bytenop, .fast_bextr, + .fast_imm16, .fast_lzcnt, .fast_movbe, .fast_scalar_fsqrt, @@ -4528,6 +4607,7 @@ pub const cpu = struct { .fma, .fsgsbase, .fxsr, + .idivq_to_divl, .lzcnt, .mmx, .movbe, @@ -4571,6 +4651,7 @@ pub const cpu = struct { .f16c, .fast_15bytenop, .fast_bextr, + .fast_imm16, .fast_lzcnt, .fast_movbe, .fast_scalar_fsqrt, @@ -4580,6 +4661,7 @@ pub const cpu = struct { .fma, .fsgsbase, .fxsr, + .idivq_to_divl, .lzcnt, .mmx, .movbe, @@ -4624,6 +4706,7 @@ pub const cpu = struct { .f16c, .fast_15bytenop, .fast_bextr, + .fast_imm16, .fast_lzcnt, .fast_movbe, .fast_scalar_fsqrt, @@ -4634,6 +4717,7 @@ pub const cpu = struct { .fsgsbase, .fsrm, .fxsr, + .idivq_to_divl, .invpcid, .lzcnt, .macrofusion, @@ -4692,6 +4776,8 @@ pub const cpu = struct { .evex512, .fast_15bytenop, .fast_bextr, + .fast_dpwssd, + .fast_imm16, .fast_lzcnt, .fast_movbe, .fast_scalar_fsqrt, @@ -4702,6 +4788,7 @@ pub const cpu = struct { .fsrm, .fxsr, .gfni, + .idivq_to_divl, .invpcid, .lzcnt, .macrofusion,