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elf+aarch64: relax TLSDESC for executables
This commit is contained in:
Jakub Konka
parent
310cef0972
commit
d9069cbe2c
@ -1633,7 +1633,7 @@ const aarch64 = struct {
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.TLSDESC_ADD_LO12,
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=> {
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const should_relax = elf_file.base.isStatic() or (!is_dyn_lib and !symbol.flags.import);
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if (!should_relax and true) { // TODO
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if (!should_relax) {
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symbol.flags.needs_tlsdesc = true;
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}
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},
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@ -1659,7 +1659,7 @@ const aarch64 = struct {
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target: *const Symbol,
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args: ResolveArgs,
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it: *RelocsIterator,
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code: []u8,
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code_buffer: []u8,
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stream: anytype,
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) (error{ UnexpectedRemainder, DivisionByZero } || RelocError)!void {
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_ = it;
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@ -1667,6 +1667,7 @@ const aarch64 = struct {
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const r_type: elf.R_AARCH64 = @enumFromInt(rel.r_type());
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const r_offset = std.math.cast(usize, rel.r_offset) orelse return error.Overflow;
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const cwriter = stream.writer();
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const code = code_buffer[rel.r_offset..][0..4];
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const P, const A, const S, const GOT, const G, const TP, const DTP, const ZIG_GOT = args;
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_ = DTP;
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@ -1700,7 +1701,7 @@ const aarch64 = struct {
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});
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return;
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};
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aarch64_util.writeBranchImm(disp, code[r_offset..][0..4]);
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aarch64_util.writeBranchImm(disp, code);
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},
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.ADR_PREL_PG_HI21 => {
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@ -1708,14 +1709,14 @@ const aarch64 = struct {
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const saddr = @as(u64, @intCast(P));
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const taddr = @as(u64, @intCast(S + A));
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const pages = @as(u21, @bitCast(try aarch64_util.calcNumberOfPages(saddr, taddr)));
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aarch64_util.writeAdrpInst(pages, code[r_offset..][0..4]);
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aarch64_util.writeAdrpInst(pages, code);
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},
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.ADR_GOT_PAGE => if (target.flags.has_got) {
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const saddr = @as(u64, @intCast(P));
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const taddr = @as(u64, @intCast(G + GOT + A));
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const pages = @as(u21, @bitCast(try aarch64_util.calcNumberOfPages(saddr, taddr)));
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aarch64_util.writeAdrpInst(pages, code[r_offset..][0..4]);
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aarch64_util.writeAdrpInst(pages, code);
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} else {
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// TODO: relax
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var err = try elf_file.addErrorWithNotes(1);
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@ -1730,12 +1731,12 @@ const aarch64 = struct {
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.LD64_GOT_LO12_NC => {
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assert(target.flags.has_got);
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const taddr = @as(u64, @intCast(G + GOT + A));
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aarch64_util.writeLoadStoreRegInst(@divExact(@as(u12, @truncate(taddr)), 8), code[rel.r_offset..][0..4]);
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aarch64_util.writeLoadStoreRegInst(@divExact(@as(u12, @truncate(taddr)), 8), code);
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},
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.ADD_ABS_LO12_NC => {
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const taddr = @as(u64, @intCast(S + A));
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aarch64_util.writeAddImmInst(@truncate(taddr), code[rel.r_offset..][0..4]);
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aarch64_util.writeAddImmInst(@truncate(taddr), code);
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},
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.LDST8_ABS_LO12_NC,
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@ -1754,48 +1755,79 @@ const aarch64 = struct {
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.LDST128_ABS_LO12_NC => @divExact(@as(u12, @truncate(taddr)), 16),
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else => unreachable,
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};
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aarch64_util.writeLoadStoreRegInst(offset, code[rel.r_offset..][0..4]);
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aarch64_util.writeLoadStoreRegInst(offset, code);
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},
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.TLSLE_ADD_TPREL_HI12 => {
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const value = math.cast(i12, (S + A - TP) >> 12) orelse
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return error.Overflow;
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aarch64_util.writeAddImmInst(@bitCast(value), code[rel.r_offset..][0..4]);
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aarch64_util.writeAddImmInst(@bitCast(value), code);
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},
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.TLSLE_ADD_TPREL_LO12_NC => {
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const value: i12 = @truncate(S + A - TP);
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aarch64_util.writeAddImmInst(@bitCast(value), code[rel.r_offset..][0..4]);
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aarch64_util.writeAddImmInst(@bitCast(value), code);
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},
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.TLSDESC_ADR_PAGE21 => {
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assert(target.flags.has_tlsdesc); // TODO relax
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const S_: i64 = @intCast(target.tlsDescAddress(elf_file));
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const saddr: u64 = @intCast(P);
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const taddr: u64 = @intCast(S_ + A);
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relocs_log.debug(" [{x} => {x}]", .{ P, taddr });
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const pages: u21 = @bitCast(try aarch64_util.calcNumberOfPages(saddr, taddr));
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aarch64_util.writeAdrpInst(pages, code[rel.r_offset..][0..4]);
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if (target.flags.has_tlsdesc) {
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const S_: i64 = @intCast(target.tlsDescAddress(elf_file));
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const saddr: u64 = @intCast(P);
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const taddr: u64 = @intCast(S_ + A);
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relocs_log.debug(" [{x} => {x}]", .{ P, taddr });
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const pages: u21 = @bitCast(try aarch64_util.calcNumberOfPages(saddr, taddr));
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aarch64_util.writeAdrpInst(pages, code);
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} else {
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relocs_log.debug(" relaxing adrp => nop", .{});
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mem.writeInt(u32, code, Instruction.nop().toU32(), .little);
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}
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},
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.TLSDESC_LD64_LO12 => {
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const S_: i64 = @intCast(target.tlsDescAddress(elf_file));
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const taddr: u64 = @intCast(S_ + A);
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relocs_log.debug(" [{x} => {x}]", .{ P, taddr });
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const offset: u12 = try math.divExact(u12, @truncate(taddr), 8);
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aarch64_util.writeLoadStoreRegInst(offset, code[rel.r_offset..][0..4]);
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if (target.flags.has_tlsdesc) {
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const S_: i64 = @intCast(target.tlsDescAddress(elf_file));
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const taddr: u64 = @intCast(S_ + A);
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relocs_log.debug(" [{x} => {x}]", .{ P, taddr });
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const offset: u12 = try math.divExact(u12, @truncate(taddr), 8);
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aarch64_util.writeLoadStoreRegInst(offset, code);
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} else {
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relocs_log.debug(" relaxing ldr => nop", .{});
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mem.writeInt(u32, code, Instruction.nop().toU32(), .little);
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}
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},
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.TLSDESC_ADD_LO12 => {
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const S_: i64 = @intCast(target.tlsDescAddress(elf_file));
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const taddr: u64 = @intCast(S_ + A);
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relocs_log.debug(" [{x} => {x}]", .{ P, taddr });
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const offset: u12 = @truncate(taddr);
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aarch64_util.writeAddImmInst(offset, code[rel.r_offset..][0..4]);
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if (target.flags.has_tlsdesc) {
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const S_: i64 = @intCast(target.tlsDescAddress(elf_file));
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const taddr: u64 = @intCast(S_ + A);
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relocs_log.debug(" [{x} => {x}]", .{ P, taddr });
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const offset: u12 = @truncate(taddr);
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aarch64_util.writeAddImmInst(offset, code);
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} else {
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const old_inst = Instruction{
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.add_subtract_immediate = mem.bytesToValue(std.meta.TagPayload(
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Instruction,
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Instruction.add_subtract_immediate,
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), code),
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};
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const rd: Register = @enumFromInt(old_inst.add_subtract_immediate.rd);
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relocs_log.debug(" relaxing add({s}) => movz(x0, {x})", .{ @tagName(rd), S + A - TP });
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const value: u16 = @bitCast(math.cast(i16, (S + A - TP) >> 16) orelse return error.Overflow);
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mem.writeInt(u32, code, Instruction.movz(.x0, value, 16).toU32(), .little);
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}
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},
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.TLSDESC_CALL => if (!target.flags.has_tlsdesc) {
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mem.writeInt(u32, code[rel.r_offset..][0..4], aarch64_util.Instruction.nop().toU32(), .little);
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const old_inst = Instruction{
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.unconditional_branch_register = mem.bytesToValue(std.meta.TagPayload(
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Instruction,
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Instruction.unconditional_branch_register,
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), code),
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};
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const rn: Register = @enumFromInt(old_inst.unconditional_branch_register.rn);
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relocs_log.debug(" relaxing br({s}) => movk(x0, {x})", .{ @tagName(rn), S + A - TP });
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const value: u16 = @bitCast(@as(i16, @truncate(S + A - TP)));
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mem.writeInt(u32, code, Instruction.movk(.x0, value, 0).toU32(), .little);
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},
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else => try atom.reportUnhandledRelocError(rel, elf_file),
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@ -1830,6 +1862,8 @@ const aarch64 = struct {
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}
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const aarch64_util = @import("../aarch64.zig");
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const Instruction = aarch64_util.Instruction;
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const Register = aarch64_util.Register;
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};
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const riscv = struct {
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