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stage2 AArch64: move cmp to new allocRegs mechanism
Remove cmp from binOp in the process
This commit is contained in:
joachimschmidt557
parent
5838fe89c1
commit
d8fddb535c
@ -1265,6 +1265,376 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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/// An argument to a Mir instruction which is read (and possibly also
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/// written to) by the respective instruction
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const ReadArg = struct {
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ty: Type,
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bind: Bind,
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class: RegisterManager.RegisterBitSet,
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reg: *Register,
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const Bind = union(enum) {
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inst: Air.Inst.Ref,
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mcv: MCValue,
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fn resolveToMcv(bind: Bind, function: *Self) InnerError!MCValue {
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return switch (bind) {
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.inst => |inst| try function.resolveInst(inst),
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.mcv => |mcv| mcv,
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};
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}
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fn resolveToImmediate(bind: Bind, function: *Self) InnerError!?u64 {
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switch (bind) {
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.inst => |inst| {
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// TODO resolve independently of inst_table
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const mcv = try function.resolveInst(inst);
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switch (mcv) {
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.immediate => |imm| return imm,
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else => return null,
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}
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},
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.mcv => |mcv| {
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switch (mcv) {
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.immediate => |imm| return imm,
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else => return null,
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}
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},
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}
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}
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};
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};
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/// An argument to a Mir instruction which is written to (but not read
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/// from) by the respective instruction
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const WriteArg = struct {
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ty: Type,
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bind: Bind,
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class: RegisterManager.RegisterBitSet,
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reg: *Register,
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const Bind = union(enum) {
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reg: Register,
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none: void,
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};
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};
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/// Holds all data necessary for enabling the potential reuse of
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/// operand registers as destinations
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const ReuseMetadata = struct {
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corresponding_inst: Air.Inst.Index,
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/// Maps every element index of read_args to the corresponding
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/// index in the Air instruction
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///
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/// When the order of read_args corresponds exactly to the order
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/// of the inputs of the Air instruction, this would be e.g.
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/// &.{ 0, 1 }. However, when the order is not the same or some
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/// inputs to the Air instruction are omitted (e.g. when they can
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/// be represented as immediates to the Mir instruction),
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/// operand_mapping should reflect that fact.
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operand_mapping: []const Liveness.OperandInt,
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};
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/// Allocate a set of registers for use as arguments for a Mir
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/// instruction
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///
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/// If the Mir instruction these registers are allocated for
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/// corresponds exactly to a single Air instruction, populate
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/// reuse_metadata in order to enable potential reuse of an operand as
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/// the destination (provided that that operand dies in this
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/// instruction).
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///
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/// Reusing an operand register as destination is the only time two
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/// arguments may share the same register. In all other cases,
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/// allocRegs guarantees that a register will never be allocated to
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/// more than one argument.
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///
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/// Furthermore, allocReg guarantees that all arguments which are
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/// already bound to registers before calling allocRegs will not
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/// change their register binding. This is done by locking these
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/// registers.
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fn allocRegs(
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self: *Self,
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read_args: []const ReadArg,
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write_args: []const WriteArg,
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reuse_metadata: ?ReuseMetadata,
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) InnerError!void {
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// Air instructions have exactly one output
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assert(!(reuse_metadata != null and write_args.len != 1)); // see note above
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// The operand mapping is a 1:1 mapping of read args to their
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// corresponding operand index in the Air instruction
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assert(!(reuse_metadata != null and reuse_metadata.?.operand_mapping.len != read_args.len)); // see note above
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const locks = try self.gpa.alloc(?RegisterLock, read_args.len + write_args.len);
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defer self.gpa.free(locks);
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const read_locks = locks[0..read_args.len];
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const write_locks = locks[read_args.len..];
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std.mem.set(?RegisterLock, locks, null);
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defer for (locks) |lock| {
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if (lock) |locked_reg| self.register_manager.unlockReg(locked_reg);
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};
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// When we reuse a read_arg as a destination, the corresponding
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// MCValue of the read_arg will be set to .dead. In that case, we
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// skip allocating this read_arg.
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var reused_read_arg: ?usize = null;
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// Lock all args which are already allocated to registers
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for (read_args) |arg, i| {
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv == .register) {
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read_locks[i] = self.register_manager.lockReg(mcv.register);
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}
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}
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for (write_args) |arg, i| {
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if (arg.bind == .reg) {
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write_locks[i] = self.register_manager.lockReg(arg.bind.reg);
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}
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}
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// Allocate registers for all args which aren't allocated to
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// registers yet
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for (read_args) |arg, i| {
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv == .register) {
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arg.reg.* = mcv.register;
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} else {
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const track_inst: ?Air.Inst.Index = switch (arg.bind) {
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.inst => |inst| Air.refToIndex(inst).?,
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else => null,
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};
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const raw_reg = try self.register_manager.allocReg(track_inst, gp);
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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read_locks[i] = self.register_manager.lockReg(arg.reg.*);
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}
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}
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if (reuse_metadata != null) {
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const inst = reuse_metadata.?.corresponding_inst;
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const operand_mapping = reuse_metadata.?.operand_mapping;
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const arg = write_args[0];
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if (arg.bind == .reg) {
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arg.reg.* = arg.bind.reg;
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} else {
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reuse_operand: for (read_args) |read_arg, i| {
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if (read_arg.bind == .inst) {
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const operand = read_arg.bind.inst;
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const mcv = try self.resolveInst(operand);
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if (mcv == .register and
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std.meta.eql(arg.class, read_arg.class) and
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self.reuseOperand(inst, operand, operand_mapping[i], mcv))
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{
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arg.reg.* = mcv.register;
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write_locks[0] = null;
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reused_read_arg = i;
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break :reuse_operand;
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}
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}
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} else {
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const raw_reg = try self.register_manager.allocReg(inst, arg.class);
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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write_locks[0] = self.register_manager.lockReg(arg.reg.*);
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}
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}
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} else {
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for (write_args) |arg, i| {
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if (arg.bind == .reg) {
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arg.reg.* = arg.bind.reg;
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} else {
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const raw_reg = try self.register_manager.allocReg(null, arg.class);
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arg.reg.* = self.registerAlias(raw_reg, arg.ty);
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write_locks[i] = self.register_manager.lockReg(arg.reg.*);
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}
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}
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}
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// For all read_args which need to be moved from non-register to
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// register, perform the move
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for (read_args) |arg, i| {
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if (reused_read_arg) |j| {
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// Check whether this read_arg was reused
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if (i == j) continue;
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}
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv != .register) {
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if (arg.bind == .inst) {
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const inst = Air.refToIndex(arg.bind.inst).?;
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// Overwrite the MCValue associated with this inst
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branch.inst_table.putAssumeCapacity(inst, .{ .register = arg.reg.* });
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// If the previous MCValue occupied some space we track, we
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// need to make sure it is marked as free now.
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switch (mcv) {
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.condition_flags => {
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assert(self.condition_flags_inst.? == inst);
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self.condition_flags_inst = null;
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},
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.register => |prev_reg| {
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assert(!self.register_manager.isRegFree(prev_reg));
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self.register_manager.freeReg(prev_reg);
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},
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else => {},
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}
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}
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try self.genSetReg(arg.ty, arg.reg.*, mcv);
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}
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}
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}
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/// Wrapper around allocRegs and addInst tailored for specific Mir
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/// instructions which are binary operations acting on two registers
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///
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/// Returns the destination register
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fn binOpRegisterNew(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) !MCValue {
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (maybe_inst) |inst| .{
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.corresponding_inst = inst,
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.operand_mapping = &.{ 0, 1 },
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add_shifted_register,
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.adds_shifted_register,
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.sub_shifted_register,
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.subs_shifted_register,
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=> .{ .rrr_imm6_shift = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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.imm6 = 0,
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.shift = .lsl,
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} },
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.mul,
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.lsl_register,
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.asr_register,
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.lsr_register,
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.sdiv,
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.udiv,
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=> .{ .rrr = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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.smull,
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.umull,
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=> .{ .rrr = .{
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.rd = dest_reg.toX(),
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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.and_shifted_register,
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.orr_shifted_register,
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.eor_shifted_register,
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=> .{ .rrr_imm6_logical_shift = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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.imm6 = 0,
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.shift = .lsl,
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// Wrapper around allocRegs and addInst tailored for specific Mir
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/// instructions which are binary operations acting on a register and
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/// an immediate
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///
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/// Returns the destination register
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fn binOpImmediateNew(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_immediate: u32,
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lhs_ty: Type,
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lhs_and_rhs_swapped: bool,
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maybe_inst: ?Air.Inst.Index,
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) !MCValue {
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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const operand_mapping: []const Liveness.OperandInt = if (lhs_and_rhs_swapped) &.{1} else &.{0};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (maybe_inst) |inst| .{
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.corresponding_inst = inst,
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.operand_mapping = operand_mapping,
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add_immediate,
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.adds_immediate,
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.sub_immediate,
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.subs_immediate,
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=> .{ .rr_imm12_sh = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.imm12 = @intCast(u12, rhs_immediate),
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} },
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.lsl_immediate,
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.asr_immediate,
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.lsr_immediate,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.shift = @intCast(u6, rhs_immediate),
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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@ -1342,7 +1712,6 @@ fn binOpRegister(
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defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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.cmp_shifted_register => undefined, // cmp has no destination register
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else => if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {
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break :blk lhs_reg;
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@ -1373,12 +1742,6 @@ fn binOpRegister(
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.imm6 = 0,
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.shift = .lsl,
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} },
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.cmp_shifted_register => .{ .rr_imm6_shift = .{
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.rn = lhs_reg,
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.rm = rhs_reg,
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.imm6 = 0,
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.shift = .lsl,
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} },
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.mul,
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.lsl_register,
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.asr_register,
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@ -1469,7 +1832,6 @@ fn binOpImmediate(
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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.cmp_immediate => undefined, // cmp has no destination register
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else => if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(
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md.inst,
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@ -1508,10 +1870,6 @@ fn binOpImmediate(
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.rn = lhs_reg,
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.shift = @intCast(u6, rhs.immediate),
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} },
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.cmp_immediate => .{ .r_imm12_sh = .{
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.rn = lhs_reg,
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.imm12 = @intCast(u12, rhs.immediate),
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} },
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else => unreachable,
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};
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@ -1554,7 +1912,6 @@ fn binOp(
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switch (tag) {
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.add,
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.sub,
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.cmp_eq,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO binary operations on floats", .{}),
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@ -1568,13 +1925,12 @@ fn binOp(
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// operands
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const lhs_immediate_ok = switch (tag) {
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.add => lhs == .immediate and lhs.immediate <= std.math.maxInt(u12),
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.sub, .cmp_eq => false,
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.sub => false,
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else => unreachable,
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};
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const rhs_immediate_ok = switch (tag) {
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.add,
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.sub,
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.cmp_eq,
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=> rhs == .immediate and rhs.immediate <= std.math.maxInt(u12),
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else => unreachable,
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};
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@ -1582,13 +1938,11 @@ fn binOp(
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.add => .add_shifted_register,
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.sub => .sub_shifted_register,
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.cmp_eq => .cmp_shifted_register,
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else => unreachable,
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};
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const mir_tag_immediate: Mir.Inst.Tag = switch (tag) {
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.add => .add_immediate,
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.sub => .sub_immediate,
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.cmp_eq => .cmp_immediate,
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else => unreachable,
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};
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@ -2052,7 +2406,15 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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try self.truncRegister(dest_reg, truncated_reg, int_info.signedness, int_info.bits);
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// cmp dest, truncated
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_ = try self.binOp(.cmp_eq, dest, .{ .register = truncated_reg }, lhs_ty, lhs_ty, null);
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_ = try self.addInst(.{
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.tag = .cmp_shifted_register,
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.data = .{ .rr_imm6_shift = .{
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.rn = dest_reg,
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.rm = truncated_reg,
|
||||
.imm6 = 0,
|
||||
.shift = .lsl,
|
||||
} },
|
||||
});
|
||||
|
||||
try self.genSetStack(lhs_ty, stack_offset, .{ .register = truncated_reg });
|
||||
try self.genSetStack(Type.initTag(.u1), stack_offset - overflow_bit_offset, .{ .condition_flags = .ne });
|
||||
@ -2333,14 +2695,13 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
|
||||
} },
|
||||
});
|
||||
|
||||
_ = try self.binOp(
|
||||
.cmp_eq,
|
||||
.{ .register = dest_high_reg },
|
||||
.{ .immediate = 0 },
|
||||
Type.usize,
|
||||
Type.usize,
|
||||
null,
|
||||
);
|
||||
_ = try self.addInst(.{
|
||||
.tag = .cmp_immediate,
|
||||
.data = .{ .r_imm12_sh = .{
|
||||
.rn = dest_high_reg,
|
||||
.imm12 = 0,
|
||||
} },
|
||||
});
|
||||
|
||||
if (int_info.bits < 64) {
|
||||
// lsr dest_high, dest, #shift
|
||||
@ -2353,14 +2714,13 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
|
||||
} },
|
||||
});
|
||||
|
||||
_ = try self.binOp(
|
||||
.cmp_eq,
|
||||
.{ .register = dest_high_reg },
|
||||
.{ .immediate = 0 },
|
||||
Type.usize,
|
||||
Type.usize,
|
||||
null,
|
||||
);
|
||||
_ = try self.addInst(.{
|
||||
.tag = .cmp_immediate,
|
||||
.data = .{ .r_imm12_sh = .{
|
||||
.rn = dest_high_reg,
|
||||
.imm12 = 0,
|
||||
} },
|
||||
});
|
||||
}
|
||||
},
|
||||
}
|
||||
@ -2388,8 +2748,6 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
|
||||
const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
|
||||
if (self.liveness.isUnused(inst)) return self.finishAir(inst, .dead, .{ extra.lhs, extra.rhs, .none });
|
||||
const result: MCValue = result: {
|
||||
const lhs = try self.resolveInst(extra.lhs);
|
||||
const rhs = try self.resolveInst(extra.rhs);
|
||||
const lhs_ty = self.air.typeOf(extra.lhs);
|
||||
const rhs_ty = self.air.typeOf(extra.rhs);
|
||||
|
||||
@ -2405,33 +2763,113 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
|
||||
if (int_info.bits <= 64) {
|
||||
const stack_offset = try self.allocMem(tuple_size, tuple_align, inst);
|
||||
|
||||
const lhs_lock: ?RegisterLock = if (lhs == .register)
|
||||
self.register_manager.lockRegAssumeUnused(lhs.register)
|
||||
else
|
||||
null;
|
||||
defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
|
||||
|
||||
try self.spillCompareFlagsIfOccupied();
|
||||
self.condition_flags_inst = null;
|
||||
|
||||
// lsl dest, lhs, rhs
|
||||
const dest = try self.binOp(.shl, lhs, rhs, lhs_ty, rhs_ty, null);
|
||||
const dest_reg = dest.register;
|
||||
const dest_reg_lock = self.register_manager.lockRegAssumeUnused(dest_reg);
|
||||
defer self.register_manager.unlockReg(dest_reg_lock);
|
||||
const lhs_bind: ReadArg.Bind = .{ .inst = extra.lhs };
|
||||
const rhs_bind: ReadArg.Bind = .{ .inst = extra.rhs };
|
||||
|
||||
// asr/lsr reconstructed, dest, rhs
|
||||
const reconstructed = try self.binOp(.shr, dest, rhs, lhs_ty, rhs_ty, null);
|
||||
var lhs_reg: Register = undefined;
|
||||
var rhs_reg: Register = undefined;
|
||||
var dest_reg: Register = undefined;
|
||||
var reconstructed_reg: Register = undefined;
|
||||
|
||||
const rhs_immediate = try rhs_bind.resolveToImmediate(self);
|
||||
if (rhs_immediate) |imm| {
|
||||
const read_args = [_]ReadArg{
|
||||
.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
|
||||
};
|
||||
const write_args = [_]WriteArg{
|
||||
.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
|
||||
.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &reconstructed_reg },
|
||||
};
|
||||
try self.allocRegs(
|
||||
&read_args,
|
||||
&write_args,
|
||||
null,
|
||||
);
|
||||
|
||||
// lsl dest, lhs, rhs
|
||||
_ = try self.addInst(.{
|
||||
.tag = .lsl_immediate,
|
||||
.data = .{ .rr_shift = .{
|
||||
.rd = dest_reg,
|
||||
.rn = lhs_reg,
|
||||
.shift = @intCast(u6, imm),
|
||||
} },
|
||||
});
|
||||
|
||||
try self.truncRegister(dest_reg, dest_reg, int_info.signedness, int_info.bits);
|
||||
|
||||
// asr/lsr reconstructed, dest, rhs
|
||||
_ = try self.addInst(.{
|
||||
.tag = switch (int_info.signedness) {
|
||||
.signed => Mir.Inst.Tag.asr_immediate,
|
||||
.unsigned => Mir.Inst.Tag.lsr_immediate,
|
||||
},
|
||||
.data = .{ .rr_shift = .{
|
||||
.rd = reconstructed_reg,
|
||||
.rn = dest_reg,
|
||||
.shift = @intCast(u6, imm),
|
||||
} },
|
||||
});
|
||||
} else {
|
||||
const read_args = [_]ReadArg{
|
||||
.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
|
||||
.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
|
||||
};
|
||||
const write_args = [_]WriteArg{
|
||||
.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
|
||||
.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &reconstructed_reg },
|
||||
};
|
||||
try self.allocRegs(
|
||||
&read_args,
|
||||
&write_args,
|
||||
null,
|
||||
);
|
||||
|
||||
// lsl dest, lhs, rhs
|
||||
_ = try self.addInst(.{
|
||||
.tag = .lsl_register,
|
||||
.data = .{ .rrr = .{
|
||||
.rd = dest_reg,
|
||||
.rn = lhs_reg,
|
||||
.rm = rhs_reg,
|
||||
} },
|
||||
});
|
||||
|
||||
try self.truncRegister(dest_reg, dest_reg, int_info.signedness, int_info.bits);
|
||||
|
||||
// asr/lsr reconstructed, dest, rhs
|
||||
_ = try self.addInst(.{
|
||||
.tag = switch (int_info.signedness) {
|
||||
.signed => Mir.Inst.Tag.asr_register,
|
||||
.unsigned => Mir.Inst.Tag.lsr_register,
|
||||
},
|
||||
.data = .{ .rrr = .{
|
||||
.rd = reconstructed_reg,
|
||||
.rn = dest_reg,
|
||||
.rm = rhs_reg,
|
||||
} },
|
||||
});
|
||||
}
|
||||
|
||||
// cmp lhs, reconstructed
|
||||
_ = try self.binOp(.cmp_eq, lhs, reconstructed, lhs_ty, lhs_ty, null);
|
||||
_ = try self.addInst(.{
|
||||
.tag = .cmp_shifted_register,
|
||||
.data = .{ .rr_imm6_shift = .{
|
||||
.rn = lhs_reg,
|
||||
.rm = reconstructed_reg,
|
||||
.imm6 = 0,
|
||||
.shift = .lsl,
|
||||
} },
|
||||
});
|
||||
|
||||
try self.genSetStack(lhs_ty, stack_offset, dest);
|
||||
try self.genSetStack(lhs_ty, stack_offset, .{ .register = dest_reg });
|
||||
try self.genSetStack(Type.initTag(.u1), stack_offset - overflow_bit_offset, .{ .condition_flags = .ne });
|
||||
|
||||
break :result MCValue{ .stack_offset = stack_offset };
|
||||
} else {
|
||||
return self.fail("TODO overflow operations on integers > u64/i64", .{});
|
||||
return self.fail("TODO ARM overflow operations on integers > u32/i32", .{});
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
@ -3634,56 +4072,102 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
|
||||
|
||||
fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
|
||||
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
||||
const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
|
||||
const lhs = try self.resolveInst(bin_op.lhs);
|
||||
const rhs = try self.resolveInst(bin_op.rhs);
|
||||
const lhs_ty = self.air.typeOf(bin_op.lhs);
|
||||
const lhs_ty = self.air.typeOf(bin_op.lhs);
|
||||
|
||||
var int_buffer: Type.Payload.Bits = undefined;
|
||||
const int_ty = switch (lhs_ty.zigTypeTag()) {
|
||||
.Vector => return self.fail("TODO AArch64 cmp vectors", .{}),
|
||||
.Enum => lhs_ty.intTagType(&int_buffer),
|
||||
.Int => lhs_ty,
|
||||
.Bool => Type.initTag(.u1),
|
||||
.Pointer => Type.usize,
|
||||
.ErrorSet => Type.initTag(.u16),
|
||||
.Optional => blk: {
|
||||
var opt_buffer: Type.Payload.ElemType = undefined;
|
||||
const payload_ty = lhs_ty.optionalChild(&opt_buffer);
|
||||
if (!payload_ty.hasRuntimeBitsIgnoreComptime()) {
|
||||
break :blk Type.initTag(.u1);
|
||||
} else if (lhs_ty.isPtrLikeOptional()) {
|
||||
break :blk Type.usize;
|
||||
} else {
|
||||
return self.fail("TODO AArch64 cmp non-pointer optionals", .{});
|
||||
}
|
||||
},
|
||||
.Float => return self.fail("TODO AArch64 cmp floats", .{}),
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
const int_info = int_ty.intInfo(self.target.*);
|
||||
if (int_info.bits <= 64) {
|
||||
_ = try self.binOp(.cmp_eq, lhs, rhs, int_ty, int_ty, BinOpMetadata{
|
||||
.inst = inst,
|
||||
.lhs = bin_op.lhs,
|
||||
.rhs = bin_op.rhs,
|
||||
});
|
||||
|
||||
try self.spillCompareFlagsIfOccupied();
|
||||
self.condition_flags_inst = inst;
|
||||
|
||||
break :result switch (int_info.signedness) {
|
||||
.signed => MCValue{ .condition_flags = Condition.fromCompareOperatorSigned(op) },
|
||||
.unsigned => MCValue{ .condition_flags = Condition.fromCompareOperatorUnsigned(op) },
|
||||
};
|
||||
} else {
|
||||
return self.fail("TODO AArch64 cmp for ints > 64 bits", .{});
|
||||
}
|
||||
const result: MCValue = if (self.liveness.isUnused(inst)) .dead else blk: {
|
||||
break :blk try self.cmp(.{ .inst = bin_op.lhs }, .{ .inst = bin_op.rhs }, lhs_ty, op);
|
||||
};
|
||||
|
||||
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
|
||||
}
|
||||
|
||||
fn cmp(
|
||||
self: *Self,
|
||||
lhs: ReadArg.Bind,
|
||||
rhs: ReadArg.Bind,
|
||||
lhs_ty: Type,
|
||||
op: math.CompareOperator,
|
||||
) !MCValue {
|
||||
var int_buffer: Type.Payload.Bits = undefined;
|
||||
const int_ty = switch (lhs_ty.zigTypeTag()) {
|
||||
.Optional => blk: {
|
||||
var opt_buffer: Type.Payload.ElemType = undefined;
|
||||
const payload_ty = lhs_ty.optionalChild(&opt_buffer);
|
||||
if (!payload_ty.hasRuntimeBitsIgnoreComptime()) {
|
||||
break :blk Type.initTag(.u1);
|
||||
} else if (lhs_ty.isPtrLikeOptional()) {
|
||||
break :blk Type.usize;
|
||||
} else {
|
||||
return self.fail("TODO ARM cmp non-pointer optionals", .{});
|
||||
}
|
||||
},
|
||||
.Float => return self.fail("TODO ARM cmp floats", .{}),
|
||||
.Enum => lhs_ty.intTagType(&int_buffer),
|
||||
.Int => lhs_ty,
|
||||
.Bool => Type.initTag(.u1),
|
||||
.Pointer => Type.usize,
|
||||
.ErrorSet => Type.initTag(.u16),
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
const int_info = int_ty.intInfo(self.target.*);
|
||||
if (int_info.bits <= 64) {
|
||||
try self.spillCompareFlagsIfOccupied();
|
||||
|
||||
var lhs_reg: Register = undefined;
|
||||
var rhs_reg: Register = undefined;
|
||||
|
||||
const rhs_immediate = try rhs.resolveToImmediate(self);
|
||||
const rhs_immediate_ok = if (rhs_immediate) |imm| imm <= std.math.maxInt(u12) else false;
|
||||
|
||||
if (rhs_immediate_ok) {
|
||||
const read_args = [_]ReadArg{
|
||||
.{ .ty = int_ty, .bind = lhs, .class = gp, .reg = &lhs_reg },
|
||||
};
|
||||
try self.allocRegs(
|
||||
&read_args,
|
||||
&.{},
|
||||
null, // we won't be able to reuse a register as there are no write_regs
|
||||
);
|
||||
|
||||
_ = try self.addInst(.{
|
||||
.tag = .cmp_immediate,
|
||||
.data = .{ .r_imm12_sh = .{
|
||||
.rn = lhs_reg,
|
||||
.imm12 = @intCast(u12, rhs_immediate.?),
|
||||
} },
|
||||
});
|
||||
} else {
|
||||
const read_args = [_]ReadArg{
|
||||
.{ .ty = int_ty, .bind = lhs, .class = gp, .reg = &lhs_reg },
|
||||
.{ .ty = int_ty, .bind = rhs, .class = gp, .reg = &rhs_reg },
|
||||
};
|
||||
try self.allocRegs(
|
||||
&read_args,
|
||||
&.{},
|
||||
null, // we won't be able to reuse a register as there are no write_regs
|
||||
);
|
||||
|
||||
_ = try self.addInst(.{
|
||||
.tag = .cmp_shifted_register,
|
||||
.data = .{ .rr_imm6_shift = .{
|
||||
.rn = lhs_reg,
|
||||
.rm = rhs_reg,
|
||||
.imm6 = 0,
|
||||
.shift = .lsl,
|
||||
} },
|
||||
});
|
||||
}
|
||||
|
||||
return switch (int_info.signedness) {
|
||||
.signed => MCValue{ .condition_flags = Condition.fromCompareOperatorSigned(op) },
|
||||
.unsigned => MCValue{ .condition_flags = Condition.fromCompareOperatorUnsigned(op) },
|
||||
};
|
||||
} else {
|
||||
return self.fail("TODO AArch64 cmp for ints > 64 bits", .{});
|
||||
}
|
||||
}
|
||||
|
||||
fn airCmpVector(self: *Self, inst: Air.Inst.Index) !void {
|
||||
_ = inst;
|
||||
return self.fail("TODO implement airCmpVector for {}", .{self.target.cpu.arch});
|
||||
@ -3926,15 +4410,13 @@ fn isNonNull(self: *Self, operand: MCValue) !MCValue {
|
||||
|
||||
fn isErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
|
||||
const error_type = ty.errorUnionSet();
|
||||
const error_int_type = Type.initTag(.u16);
|
||||
|
||||
if (error_type.errorSetIsEmpty()) {
|
||||
return MCValue{ .immediate = 0 }; // always false
|
||||
}
|
||||
|
||||
const error_mcv = try self.errUnionErr(operand, ty);
|
||||
_ = try self.binOp(.cmp_eq, error_mcv, .{ .immediate = 0 }, error_int_type, error_int_type, null);
|
||||
return MCValue{ .condition_flags = .hi };
|
||||
return try self.cmp(.{ .mcv = error_mcv }, .{ .mcv = .{ .immediate = 0 } }, error_type, .gt);
|
||||
}
|
||||
|
||||
fn isNonErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user