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https://github.com/ziglang/zig.git
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x86_64: implement @min and @max for 128-bit integers
This commit is contained in:
Jacob Young
parent
21948d7540
commit
d559c61902
@ -1120,7 +1120,7 @@ fn addExtraAssumeCapacity(self: *Self, extra: anytype) u32 {
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}
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/// A `cc` of `.z_and_np` clobbers `reg2`!
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fn asmCmovccRegisterRegister(self: *Self, reg1: Register, reg2: Register, cc: bits.Condition) !void {
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fn asmCmovccRegisterRegister(self: *Self, cc: bits.Condition, reg1: Register, reg2: Register) !void {
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_ = try self.addInst(.{
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.tag = switch (cc) {
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else => .cmov,
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@ -1143,7 +1143,7 @@ fn asmCmovccRegisterRegister(self: *Self, reg1: Register, reg2: Register, cc: bi
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}
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/// A `cc` of `.z_and_np` is not supported by this encoding!
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fn asmCmovccRegisterMemory(self: *Self, reg: Register, m: Memory, cc: bits.Condition) !void {
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fn asmCmovccRegisterMemory(self: *Self, cc: bits.Condition, reg: Register, m: Memory) !void {
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_ = try self.addInst(.{
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.tag = switch (cc) {
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else => .cmov,
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@ -3232,9 +3232,9 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2);
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try self.asmCmovccRegisterRegister(
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cc,
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registerAlias(dst_reg, cmov_abi_size),
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registerAlias(limit_reg, cmov_abi_size),
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cc,
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);
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if (reg_extra_bits > 0 and ty.isSignedInt(mod)) {
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@ -3308,9 +3308,9 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
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const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2);
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try self.asmCmovccRegisterRegister(
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cc,
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registerAlias(dst_reg, cmov_abi_size),
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registerAlias(limit_reg, cmov_abi_size),
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cc,
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);
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if (reg_extra_bits > 0 and ty.isSignedInt(mod)) {
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@ -3371,9 +3371,9 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
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const dst_mcv = try self.genMulDivBinOp(.mul, inst, ty, ty, lhs_mcv, rhs_mcv);
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const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2);
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try self.asmCmovccRegisterRegister(
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cc,
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registerAlias(dst_mcv.register, cmov_abi_size),
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registerAlias(limit_reg, cmov_abi_size),
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cc,
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);
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return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
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@ -3743,9 +3743,9 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
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registerAlias(.rdx, abi_size),
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);
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try self.asmCmovccRegisterRegister(
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.z,
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registerAlias(divisor, abi_size),
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registerAlias(.rdx, abi_size),
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.z,
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);
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try self.genBinOpMir(.{ ._, .add }, ty, .{ .register = divisor }, .{ .register = .rax });
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return MCValue{ .register = divisor };
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@ -4626,7 +4626,7 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
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tmp_mcv,
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mat_src_mcv.address().offset(8).deref(),
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);
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try self.asmCmovccRegisterRegister(dst_reg.to32(), tmp_reg.to32(), .nc);
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try self.asmCmovccRegisterRegister(.nc, dst_reg.to32(), tmp_reg.to32());
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if (src_bits < 128) {
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try self.genBinOpMir(
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@ -4660,9 +4660,9 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
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const cmov_abi_size = @max(@as(u32, @intCast(dst_ty.abiSize(mod))), 2);
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try self.asmCmovccRegisterRegister(
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.z,
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registerAlias(dst_reg, cmov_abi_size),
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registerAlias(imm_reg, cmov_abi_size),
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.z,
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);
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try self.genBinOpMir(.{ ._, .xor }, dst_ty, dst_mcv, .{ .immediate = src_bits - 1 });
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@ -4687,9 +4687,9 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
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const cmov_abi_size = @max(@as(u32, @intCast(dst_ty.abiSize(mod))), 2);
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try self.asmCmovccRegisterRegister(
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.nz,
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registerAlias(imm_reg, cmov_abi_size),
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registerAlias(dst_reg, cmov_abi_size),
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.nz,
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);
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try self.genSetReg(dst_reg, dst_ty, .{ .immediate = src_bits - 1 });
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@ -4764,7 +4764,7 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
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try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, dst_mcv, masked_mcv);
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try self.genBinOpMir(.{ ._, .add }, dst_ty, dst_mcv, .{ .immediate = 64 });
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try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, tmp_mcv, mat_src_mcv);
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try self.asmCmovccRegisterRegister(dst_reg.to32(), tmp_reg.to32(), .nc);
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try self.asmCmovccRegisterRegister(.nc, dst_reg.to32(), tmp_reg.to32());
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} else return self.fail("TODO airCtz of {}", .{src_ty.fmt(mod)});
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break :result dst_mcv;
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}
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@ -4786,9 +4786,9 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
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const cmov_abi_size = @max(@as(u32, @intCast(dst_ty.abiSize(mod))), 2);
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try self.asmCmovccRegisterRegister(
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.z,
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registerAlias(dst_reg, cmov_abi_size),
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registerAlias(width_reg, cmov_abi_size),
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.z,
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);
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break :result dst_mcv;
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};
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@ -5400,21 +5400,21 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {
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const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2);
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switch (src_mcv) {
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.register => |val_reg| try self.asmCmovccRegisterRegister(
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.l,
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registerAlias(dst_mcv.register, cmov_abi_size),
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registerAlias(val_reg, cmov_abi_size),
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.l,
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),
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.memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory(
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.l,
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registerAlias(dst_mcv.register, cmov_abi_size),
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src_mcv.mem(Memory.PtrSize.fromSize(cmov_abi_size)),
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.l,
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),
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else => {
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const val_reg = try self.copyToTmpRegister(ty, src_mcv);
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try self.asmCmovccRegisterRegister(
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.l,
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registerAlias(dst_mcv.register, cmov_abi_size),
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registerAlias(val_reg, cmov_abi_size),
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.l,
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);
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},
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}
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@ -6605,11 +6605,11 @@ fn genShiftBinOpMir(
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Immediate.u(64),
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);
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try self.asmCmovccRegisterRegister(
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.ae,
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lhs_regs[info.indices[1]],
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lhs_regs[info.indices[0]],
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.ae,
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);
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try self.asmCmovccRegisterRegister(lhs_regs[info.indices[0]], tmp_reg, .ae);
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try self.asmCmovccRegisterRegister(.ae, lhs_regs[info.indices[0]], tmp_reg);
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},
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else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
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@tagName(lhs_mcv),
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@ -6737,8 +6737,8 @@ fn genShiftBinOpMir(
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registerAlias(rhs_reg, 1),
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Immediate.u(64),
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);
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try self.asmCmovccRegisterRegister(second_reg, first_reg, .ae);
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try self.asmCmovccRegisterRegister(first_reg, tmp_reg, .ae);
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try self.asmCmovccRegisterRegister(.ae, second_reg, first_reg);
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try self.asmCmovccRegisterRegister(.ae, first_reg, tmp_reg);
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try self.asmMemoryRegister(
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.{ ._, .mov },
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Memory.sib(.qword, .{
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@ -7138,17 +7138,22 @@ fn genBinOp(
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.Float, .Vector => true,
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};
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const lhs_lock: ?RegisterLock = switch (lhs_mcv) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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const lhs_locks: [2]?RegisterLock = switch (lhs_mcv) {
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.register => |lhs_reg| .{ self.register_manager.lockRegAssumeUnused(lhs_reg), null },
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.register_pair => |lhs_regs| locks: {
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const locks = self.register_manager.lockRegsAssumeUnused(2, lhs_regs);
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break :locks .{ locks[0], locks[1] };
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},
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else => .{ null, null },
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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defer for (lhs_locks) |lhs_lock| if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs_lock: ?RegisterLock = switch (rhs_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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const rhs_locks: [2]?RegisterLock = switch (rhs_mcv) {
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.register => |rhs_reg| .{ self.register_manager.lockReg(rhs_reg), null },
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.register_pair => |rhs_regs| self.register_manager.lockRegs(2, rhs_regs),
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else => .{ null, null },
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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defer for (rhs_locks) |rhs_lock| if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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var flipped = false;
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var copied_to_dst = true;
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@ -7171,11 +7176,12 @@ fn genBinOp(
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try self.genCopy(lhs_ty, dst_mcv, lhs_mcv);
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break :dst dst_mcv;
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};
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const dst_lock: ?RegisterLock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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const dst_locks: [2]?RegisterLock = switch (dst_mcv) {
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.register => |dst_reg| .{ self.register_manager.lockReg(dst_reg), null },
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.register_pair => |dst_regs| self.register_manager.lockRegs(2, dst_regs),
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else => .{ null, null },
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};
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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defer for (dst_locks) |dst_lock| if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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const unmat_src_mcv = if (flipped) lhs_mcv else rhs_mcv;
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const src_mcv: MCValue = if (maybe_mask_reg) |mask_reg|
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@ -7186,6 +7192,12 @@ fn genBinOp(
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}
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else
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unmat_src_mcv;
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const src_locks: [2]?RegisterLock = switch (src_mcv) {
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.register => |src_reg| .{ self.register_manager.lockReg(src_reg), null },
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.register_pair => |src_regs| self.register_manager.lockRegs(2, src_regs),
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else => .{ null, null },
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};
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defer for (src_locks) |src_lock| if (src_lock) |lock| self.register_manager.unlockReg(lock);
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if (!vec_op) {
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switch (air_tag) {
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@ -7236,102 +7248,166 @@ fn genBinOp(
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else => src_mcv,
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.air_ref => |src_ref| try self.resolveInst(src_ref),
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};
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const mat_src_mcv: MCValue = if (switch (resolved_src_mcv) {
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.immediate,
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.eflags,
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.register_offset,
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.load_direct,
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.lea_direct,
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.load_got,
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.lea_got,
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.load_tlv,
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.lea_tlv,
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.lea_frame,
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=> true,
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.memory => |addr| math.cast(i32, @as(i64, @bitCast(addr))) == null,
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else => false,
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.register_pair,
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.register_overflow,
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=> unreachable,
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})
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.{ .register = try self.copyToTmpRegister(rhs_ty, resolved_src_mcv) }
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else
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resolved_src_mcv;
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const mat_mcv_lock = switch (mat_src_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (mat_mcv_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genBinOpMir(.{ ._, .cmp }, lhs_ty, dst_mcv, mat_src_mcv);
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if (abi_size > 8) {
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const dst_regs = switch (dst_mcv) {
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.register_pair => |dst_regs| dst_regs,
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else => dst: {
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const dst_regs = try self.register_manager.allocRegs(
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2,
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.{ null, null },
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abi.RegisterClass.gp,
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);
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const dst_regs_locks = self.register_manager.lockRegs(2, dst_regs);
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for (dst_regs_locks) |dst_lock| if (dst_lock) |lock|
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self.register_manager.unlockReg(lock);
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const int_info = lhs_ty.intInfo(mod);
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const cc: Condition = switch (int_info.signedness) {
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.unsigned => switch (air_tag) {
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.min => .a,
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.max => .b,
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try self.genCopy(lhs_ty, .{ .register_pair = dst_regs }, dst_mcv);
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break :dst dst_regs;
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},
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};
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const dst_regs_locks = self.register_manager.lockRegs(2, dst_regs);
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for (dst_regs_locks) |dst_lock| if (dst_lock) |lock|
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self.register_manager.unlockReg(lock);
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const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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const signed = lhs_ty.isSignedInt(mod);
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const cc: Condition = switch (air_tag) {
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.min => if (signed) .nl else .nb,
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.max => if (signed) .nge else .nae,
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else => unreachable,
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},
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.signed => switch (air_tag) {
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.min => .g,
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.max => .l,
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else => unreachable,
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},
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};
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};
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const cmov_abi_size = @max(@as(u32, @intCast(lhs_ty.abiSize(mod))), 2);
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const tmp_reg = switch (dst_mcv) {
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.register => |reg| reg,
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else => try self.copyToTmpRegister(lhs_ty, dst_mcv),
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};
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const tmp_lock = self.register_manager.lockReg(tmp_reg);
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defer if (tmp_lock) |lock| self.register_manager.unlockReg(lock);
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switch (mat_src_mcv) {
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.none,
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.unreach,
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.dead,
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.undef,
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.immediate,
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.eflags,
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.register_pair,
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.register_offset,
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.register_overflow,
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.load_direct,
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.lea_direct,
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.load_got,
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.lea_got,
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.load_tlv,
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.lea_tlv,
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.lea_frame,
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.reserved_frame,
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.air_ref,
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=> unreachable,
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.register => |src_reg| try self.asmCmovccRegisterRegister(
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registerAlias(tmp_reg, cmov_abi_size),
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registerAlias(src_reg, cmov_abi_size),
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cc,
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),
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.memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory(
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registerAlias(tmp_reg, cmov_abi_size),
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Memory.sib(Memory.PtrSize.fromSize(cmov_abi_size), switch (mat_src_mcv) {
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.memory => |addr| .{
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.base = .{ .reg = .ds },
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.disp = @intCast(@as(i64, @bitCast(addr))),
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},
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.indirect => |reg_off| .{
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.base = .{ .reg = reg_off.reg },
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.disp = reg_off.off,
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},
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.load_frame => |frame_addr| .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off,
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},
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try self.asmRegisterRegister(.{ ._, .mov }, tmp_reg, dst_regs[1]);
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if (src_mcv.isMemory()) {
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try self.asmRegisterMemory(.{ ._, .cmp }, dst_regs[0], src_mcv.mem(.qword));
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try self.asmRegisterMemory(
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.{ ._, .sbb },
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tmp_reg,
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src_mcv.address().offset(8).deref().mem(.qword),
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);
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try self.asmCmovccRegisterMemory(cc, dst_regs[0], src_mcv.mem(.qword));
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try self.asmCmovccRegisterMemory(
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cc,
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dst_regs[1],
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src_mcv.address().offset(8).deref().mem(.qword),
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);
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} else {
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try self.asmRegisterRegister(
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.{ ._, .cmp },
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dst_regs[0],
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src_mcv.register_pair[0],
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);
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try self.asmRegisterRegister(
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.{ ._, .sbb },
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tmp_reg,
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src_mcv.register_pair[1],
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);
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try self.asmCmovccRegisterRegister(cc, dst_regs[0], src_mcv.register_pair[0]);
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try self.asmCmovccRegisterRegister(cc, dst_regs[1], src_mcv.register_pair[1]);
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}
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try self.genCopy(lhs_ty, dst_mcv, .{ .register_pair = dst_regs });
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} else {
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const mat_src_mcv: MCValue = if (switch (resolved_src_mcv) {
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.immediate,
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.eflags,
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.register_offset,
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.load_direct,
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.lea_direct,
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.load_got,
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.lea_got,
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.load_tlv,
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.lea_tlv,
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.lea_frame,
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=> true,
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.memory => |addr| math.cast(i32, @as(i64, @bitCast(addr))) == null,
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else => false,
|
||||
.register_pair,
|
||||
.register_overflow,
|
||||
=> unreachable,
|
||||
})
|
||||
.{ .register = try self.copyToTmpRegister(rhs_ty, resolved_src_mcv) }
|
||||
else
|
||||
resolved_src_mcv;
|
||||
const mat_mcv_lock = switch (mat_src_mcv) {
|
||||
.register => |reg| self.register_manager.lockReg(reg),
|
||||
else => null,
|
||||
};
|
||||
defer if (mat_mcv_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
|
||||
try self.genBinOpMir(.{ ._, .cmp }, lhs_ty, dst_mcv, mat_src_mcv);
|
||||
|
||||
const int_info = lhs_ty.intInfo(mod);
|
||||
const cc: Condition = switch (int_info.signedness) {
|
||||
.unsigned => switch (air_tag) {
|
||||
.min => .a,
|
||||
.max => .b,
|
||||
else => unreachable,
|
||||
}),
|
||||
cc,
|
||||
),
|
||||
},
|
||||
.signed => switch (air_tag) {
|
||||
.min => .g,
|
||||
.max => .l,
|
||||
else => unreachable,
|
||||
},
|
||||
};
|
||||
|
||||
const cmov_abi_size = @max(@as(u32, @intCast(lhs_ty.abiSize(mod))), 2);
|
||||
const tmp_reg = switch (dst_mcv) {
|
||||
.register => |reg| reg,
|
||||
else => try self.copyToTmpRegister(lhs_ty, dst_mcv),
|
||||
};
|
||||
const tmp_lock = self.register_manager.lockReg(tmp_reg);
|
||||
defer if (tmp_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
switch (mat_src_mcv) {
|
||||
.none,
|
||||
.unreach,
|
||||
.dead,
|
||||
.undef,
|
||||
.immediate,
|
||||
.eflags,
|
||||
.register_pair,
|
||||
.register_offset,
|
||||
.register_overflow,
|
||||
.load_direct,
|
||||
.lea_direct,
|
||||
.load_got,
|
||||
.lea_got,
|
||||
.load_tlv,
|
||||
.lea_tlv,
|
||||
.lea_frame,
|
||||
.reserved_frame,
|
||||
.air_ref,
|
||||
=> unreachable,
|
||||
.register => |src_reg| try self.asmCmovccRegisterRegister(
|
||||
cc,
|
||||
registerAlias(tmp_reg, cmov_abi_size),
|
||||
registerAlias(src_reg, cmov_abi_size),
|
||||
),
|
||||
.memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory(
|
||||
cc,
|
||||
registerAlias(tmp_reg, cmov_abi_size),
|
||||
Memory.sib(Memory.PtrSize.fromSize(cmov_abi_size), switch (mat_src_mcv) {
|
||||
.memory => |addr| .{
|
||||
.base = .{ .reg = .ds },
|
||||
.disp = @intCast(@as(i64, @bitCast(addr))),
|
||||
},
|
||||
.indirect => |reg_off| .{
|
||||
.base = .{ .reg = reg_off.reg },
|
||||
.disp = reg_off.off,
|
||||
},
|
||||
.load_frame => |frame_addr| .{
|
||||
.base = .{ .frame = frame_addr.index },
|
||||
.disp = frame_addr.off,
|
||||
},
|
||||
else => unreachable,
|
||||
}),
|
||||
),
|
||||
}
|
||||
try self.genCopy(lhs_ty, dst_mcv, .{ .register = tmp_reg });
|
||||
}
|
||||
try self.genCopy(lhs_ty, dst_mcv, .{ .register = tmp_reg });
|
||||
},
|
||||
|
||||
else => return self.fail("TODO implement genBinOp for {s} {}", .{
|
||||
@ -12053,21 +12129,21 @@ fn atomicOp(
|
||||
const cmov_abi_size = @max(val_abi_size, 2);
|
||||
switch (val_mcv) {
|
||||
.register => |val_reg| try self.asmCmovccRegisterRegister(
|
||||
cc,
|
||||
registerAlias(tmp_reg, cmov_abi_size),
|
||||
registerAlias(val_reg, cmov_abi_size),
|
||||
cc,
|
||||
),
|
||||
.memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory(
|
||||
cc,
|
||||
registerAlias(tmp_reg, cmov_abi_size),
|
||||
val_mcv.mem(Memory.PtrSize.fromSize(cmov_abi_size)),
|
||||
cc,
|
||||
),
|
||||
else => {
|
||||
const val_reg = try self.copyToTmpRegister(val_ty, val_mcv);
|
||||
try self.asmCmovccRegisterRegister(
|
||||
cc,
|
||||
registerAlias(tmp_reg, cmov_abi_size),
|
||||
registerAlias(val_reg, cmov_abi_size),
|
||||
cc,
|
||||
);
|
||||
},
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user