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Make sure that ZigTypeVector and ZigTypeArray have the same memory layout

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Throughout the stage1 code it is assumed that these have the same layout,
but that was not the case. This caused an issue on 32-bit hardware.
This commit is contained in:
Timon Kruiper 2020-04-01 20:42:43 +02:00
parent ae6965a4e7
commit d33766e6c7
4 changed files with 10 additions and 3 deletions
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8
src/all_types.hpp
View File

@ -1324,6 +1324,7 @@ struct ZigTypeFloat {
size_t bit_count;
};
// Needs to have the same memory layout as ZigTypeVector
struct ZigTypeArray {
ZigType *child_type;
uint64_t len;
@ -1512,12 +1513,17 @@ struct ZigTypeBoundFn {
ZigType *fn_type;
};
// Needs to have the same memory layout as ZigTypeArray
struct ZigTypeVector {
// The type must be a pointer, integer, bool, or float
ZigType *elem_type;
uint32_t len;
uint64_t len;
size_t padding;
};
// A lot of code is relying on ZigTypeArray and ZigTypeVector having the same layout/size
static_assert(sizeof(ZigTypeVector) == sizeof(ZigTypeArray), "Size of ZigTypeVector and ZigTypeArray do not match!");
enum ZigTypeId {
ZigTypeIdInvalid,
ZigTypeIdMetaType,

1
src/analyze.cpp
View File

@ -5156,6 +5156,7 @@ ZigType *get_vector_type(CodeGen *g, uint32_t len, ZigType *elem_type) {
}
entry->data.vector.len = len;
entry->data.vector.elem_type = elem_type;
entry->data.vector.padding = 0;
buf_resize(&entry->name, 0);
buf_appendf(&entry->name, "@Vector(%u, %s)", len, buf_ptr(&elem_type->name));

2
src/codegen.cpp
View File

@ -714,7 +714,7 @@ static LLVMValueRef get_arithmetic_overflow_fn(CodeGen *g, ZigType *operand_type
};
if (operand_type->id == ZigTypeIdVector) {
sprintf(fn_name, "llvm.%s.with.overflow.v%" PRIu32 "i%" PRIu32, signed_str,
sprintf(fn_name, "llvm.%s.with.overflow.v%" PRIu64 "i%" PRIu32, signed_str,
operand_type->data.vector.len, int_type->data.integral.bit_count);
LLVMTypeRef return_elem_types[] = {

2
src/ir.cpp
View File

@ -15953,7 +15953,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, IrInst *source_i
if (op1->value->type->id == ZigTypeIdVector && op2->value->type->id == ZigTypeIdVector) {
if (op1->value->type->data.vector.len != op2->value->type->data.vector.len) {
ir_add_error(ira, source_instr,
buf_sprintf("vector length mismatch: %" PRIu32 " and %" PRIu32,
buf_sprintf("vector length mismatch: %" PRIu64 " and %" PRIu64,
op1->value->type->data.vector.len, op2->value->type->data.vector.len));
return ira->codegen->invalid_inst_gen;
}