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Merge pull request #25886 from alexrp/kvx

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beginnings of KVX target support (via CBE)
This commit is contained in:
Alex Rønne Petersen 2025-11-10 16:38:23 +01:00 committed by GitHub
commit d182c7e3bc
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GPG Key ID: B5690EEEBB952194
16 changed files with 776 additions and 7 deletions
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5
lib/compiler/aro/aro/target.zig vendored
View File

@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.ve,
.bpfel,
.bpfeb,
.kvx,
.s390x,
=> return null,
@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.nvptx64,
.wasm64,
.spirv64,
.kvx,
.loongarch64,
.mips64,
.mips64el,
@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.ve => "ve",
// Note: propeller1, kalimba and or1k are not supported in LLVM; this is the Zig arch name
// Note: propeller1, kalimba, kvx, and or1k are not supported in LLVM; this is the Zig arch name
.kalimba => "kalimba",
.kvx => "kvx",
.propeller => "propeller",
.or1k => "or1k",
};

35
lib/std/Target.zig
View File

@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig");
pub const hexagon = @import("Target/hexagon.zig");
pub const hppa = @import("Target/generic.zig");
pub const kalimba = @import("Target/generic.zig");
pub const kvx = @import("Target/kvx.zig");
pub const lanai = @import("Target/lanai.zig");
pub const loongarch = @import("Target/loongarch.zig");
pub const m68k = @import("Target/m68k.zig");
@ -1035,7 +1036,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
.aarch64, .aarch64_be => .AARCH64,
.alpha => .ALPHA,
.amdgcn => .AMDGPU,
.arc, .arceb => .ARC_COMPACT,
.arc, .arceb => .ARC_COMPACT2,
.arm, .armeb, .thumb, .thumbeb => .ARM,
.avr => .AVR,
.bpfeb, .bpfel => .BPF,
@ -1043,6 +1044,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
.hexagon => .QDSP6,
.hppa, .hppa64 => .PARISC,
.kalimba => .CSR_KALIMBA,
.kvx => .KVX,
.lanai => .LANAI,
.loongarch32, .loongarch64 => .LOONGARCH,
.m68k => .@"68K",
@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
.hppa,
.hppa64,
.kalimba,
.kvx,
.lanai,
.m68k,
.microblaze,
@ -1310,6 +1313,7 @@ pub const Cpu = struct {
hppa,
hppa64,
kalimba,
kvx,
lanai,
loongarch32,
loongarch64,
@ -1385,6 +1389,7 @@ pub const Cpu = struct {
hexagon,
hppa,
kalimba,
kvx,
lanai,
loongarch,
m68k,
@ -1420,6 +1425,7 @@ pub const Cpu = struct {
.hexagon => .hexagon,
.hppa, .hppa64 => .hppa,
.kalimba => .kalimba,
.kvx => .kvx,
.lanai => .lanai,
.loongarch32, .loongarch64 => .loongarch,
.m68k => .m68k,
@ -1623,6 +1629,7 @@ pub const Cpu = struct {
.csky,
.hexagon,
.kalimba,
.kvx,
.loongarch32,
.loongarch64,
.microblazeel,
@ -1847,6 +1854,10 @@ pub const Cpu = struct {
.hppa64_elf,
=> &.{.hppa64},
.kvx_lp64,
.kvx_ilp32,
=> &.{.kvx},
.lanai_sysv,
=> &.{.lanai},
@ -1936,6 +1947,7 @@ pub const Cpu = struct {
return switch (arch) {
.amdgcn => &amdgcn.cpu.gfx600,
.avr => &avr.cpu.avr1,
.kvx => &kvx.cpu.coolidge_v1,
.loongarch32 => &loongarch.cpu.generic_la32,
.loongarch64 => &loongarch.cpu.generic_la64,
.mips, .mipsel => &mips.cpu.mips32,
@ -1987,6 +1999,7 @@ pub const Cpu = struct {
.bpfel, .bpfeb => &bpf.cpu.v3,
.csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
.hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
.kvx => &kvx.cpu.coolidge_v2,
.lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
.loongarch64 => &loongarch.cpu.la64v1_0,
.m68k => &m68k.cpu.M68000,
@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct {
.aarch64,
.aarch64_be,
.hexagon,
.kvx,
.m68k,
.microblaze,
.microblazeel,
@ -2666,16 +2680,20 @@ pub const DynamicLinker = struct {
},
.netbsd => switch (cpu.arch) {
.alpha,
.arm,
.armeb,
.aarch64,
.aarch64_be,
.hppa,
.m68k,
.mips,
.mipsel,
.mips64,
.mips64el,
.powerpc,
.sh,
.sheb,
.sparc,
.sparc64,
.x86,
@ -2685,13 +2703,17 @@ pub const DynamicLinker = struct {
},
.openbsd => switch (cpu.arch) {
.alpha,
.arm,
.aarch64,
.hppa,
.mips64,
.mips64el,
.powerpc,
.powerpc64,
.riscv64,
.sh,
.sheb,
.sparc64,
.x86,
.x86_64,
@ -2817,6 +2839,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
.bpfeb,
.bpfel,
.hppa64,
.kvx,
.loongarch64,
.mips64,
.mips64el,
@ -2870,6 +2893,7 @@ pub fn stackAlignment(target: *const Target) u16 {
.ve,
.wasm32,
.wasm64,
.x86_64,
=> return 16,
// Some of the following prongs should really be testing the ABI, but our current `Abi` enum
// can't handle that level of nuance yet.
@ -2882,7 +2906,7 @@ pub fn stackAlignment(target: *const Target) u16 {
.riscv64be,
=> if (!target.cpu.has(.riscv, .e)) return 16,
.x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16,
.x86_64 => return 16,
.kvx => return 32,
else => {},
}
@ -3375,6 +3399,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
.aarch64_be,
.alpha,
.hppa64,
.kvx,
.loongarch32,
.loongarch64,
.mips64,
@ -3482,6 +3507,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
.aarch64_be,
.alpha,
.hppa64,
.kvx,
.loongarch32,
.loongarch64,
.mips64,
@ -3557,6 +3583,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
.bpfel,
.bpfeb,
.hppa64,
.kvx,
.loongarch64,
.mips64,
.mips64el,
@ -3626,6 +3653,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
.hppa => .{ .hppa_elf = .{} },
.hppa64 => .{ .hppa64_elf = .{} },
.kalimba => null,
.kvx => switch (target.abi) {
.ilp32 => .{ .kvx_ilp32 = .{} },
else => .{ .kvx_lp64 = .{} },
},
.lanai => .{ .lanai_sysv = .{} },
.loongarch64 => .{ .loongarch64_lp64 = .{} },
.loongarch32 => .{ .loongarch32_ilp32 = .{} },

64
lib/std/Target/kvx.zig Normal file
View File

@ -0,0 +1,64 @@
//! This file is auto-generated by tools/update_cpu_features.zig.
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
v3_1,
v3_2,
v4_1,
};
pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
pub const all_features = blk: {
const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
result[@intFromEnum(Feature.v3_1)] = .{
.llvm_name = null,
.description = "Enable ISA v3.1",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.v3_2)] = .{
.llvm_name = null,
.description = "Enable ISA v3.2",
.dependencies = featureSet(&[_]Feature{
.v3_1,
}),
};
result[@intFromEnum(Feature.v4_1)] = .{
.llvm_name = null,
.description = "Enable ISA v4.1",
.dependencies = featureSet(&[_]Feature{
.v3_2,
}),
};
const ti = @typeInfo(Feature);
for (&result, 0..) |*elem, i| {
elem.index = i;
elem.name = ti.@"enum".fields[i].name;
}
break :blk result;
};
pub const cpu = struct {
pub const coolidge_v1: CpuModel = .{
.name = "coolidge_v1",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.v3_1,
}),
};
pub const coolidge_v2: CpuModel = .{
.name = "coolidge_v2",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.v3_2,
}),
};
};

4
lib/std/builtin.zig
View File

@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) {
/// The standard `hppa64` calling convention.
hppa64_elf: CommonOptions,
kvx_lp64: CommonOptions,
kvx_ilp32: CommonOptions,
/// The standard `lanai` calling convention.
lanai_sysv: CommonOptions,
@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) {
.csky,
.hppa,
.hppa64,
.kvx,
.lanai,
.loongarch32,
.loongarch64,

529
lib/std/builtin/assembly.zig
View File

@ -857,6 +857,535 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
f14: bool = false,
f15: bool = false,
},
.kvx => packed struct {
/// Whether the inline assembly code may perform stores to memory
/// addresses other than those derived from input pointer provenance.
memory: bool = false,
cs: bool = false,
ra: bool = false,
ls: bool = false,
le: bool = false,
lc: bool = false,
r0: bool = false,
r1: bool = false,
r2: bool = false,
r3: bool = false,
r4: bool = false,
r5: bool = false,
r6: bool = false,
r7: bool = false,
r8: bool = false,
r9: bool = false,
r10: bool = false,
r11: bool = false,
r12: bool = false,
r13: bool = false,
r14: bool = false,
r15: bool = false,
r16: bool = false,
r17: bool = false,
r18: bool = false,
r19: bool = false,
r20: bool = false,
r21: bool = false,
r22: bool = false,
r23: bool = false,
r24: bool = false,
r25: bool = false,
r26: bool = false,
r27: bool = false,
r28: bool = false,
r29: bool = false,
r30: bool = false,
r31: bool = false,
r32: bool = false,
r33: bool = false,
r34: bool = false,
r35: bool = false,
r36: bool = false,
r37: bool = false,
r38: bool = false,
r39: bool = false,
r40: bool = false,
r41: bool = false,
r42: bool = false,
r43: bool = false,
r44: bool = false,
r45: bool = false,
r46: bool = false,
r47: bool = false,
r48: bool = false,
r49: bool = false,
r50: bool = false,
r51: bool = false,
r52: bool = false,
r53: bool = false,
r54: bool = false,
r55: bool = false,
r56: bool = false,
r57: bool = false,
r58: bool = false,
r59: bool = false,
r60: bool = false,
r61: bool = false,
r62: bool = false,
r63: bool = false,
a0: bool = false,
a1: bool = false,
a2: bool = false,
a3: bool = false,
a4: bool = false,
a5: bool = false,
a6: bool = false,
a7: bool = false,
a8: bool = false,
a9: bool = false,
a10: bool = false,
a11: bool = false,
a12: bool = false,
a13: bool = false,
a14: bool = false,
a15: bool = false,
a16: bool = false,
a17: bool = false,
a18: bool = false,
a19: bool = false,
a20: bool = false,
a21: bool = false,
a22: bool = false,
a23: bool = false,
a24: bool = false,
a25: bool = false,
a26: bool = false,
a27: bool = false,
a28: bool = false,
a29: bool = false,
a30: bool = false,
a31: bool = false,
a32: bool = false,
a33: bool = false,
a34: bool = false,
a35: bool = false,
a36: bool = false,
a37: bool = false,
a38: bool = false,
a39: bool = false,
a40: bool = false,
a41: bool = false,
a42: bool = false,
a43: bool = false,
a44: bool = false,
a45: bool = false,
a46: bool = false,
a47: bool = false,
a48: bool = false,
a49: bool = false,
a50: bool = false,
a51: bool = false,
a52: bool = false,
a53: bool = false,
a54: bool = false,
a55: bool = false,
a56: bool = false,
a57: bool = false,
a58: bool = false,
a59: bool = false,
a60: bool = false,
a61: bool = false,
a62: bool = false,
a63: bool = false,
a0_lo: bool = false,
a0_hi: bool = false,
a1_lo: bool = false,
a1_hi: bool = false,
a2_lo: bool = false,
a2_hi: bool = false,
a3_lo: bool = false,
a3_hi: bool = false,
a4_lo: bool = false,
a4_hi: bool = false,
a5_lo: bool = false,
a5_hi: bool = false,
a6_lo: bool = false,
a6_hi: bool = false,
a7_lo: bool = false,
a7_hi: bool = false,
a8_lo: bool = false,
a8_hi: bool = false,
a9_lo: bool = false,
a9_hi: bool = false,
a10_lo: bool = false,
a10_hi: bool = false,
a11_lo: bool = false,
a11_hi: bool = false,
a12_lo: bool = false,
a12_hi: bool = false,
a13_lo: bool = false,
a13_hi: bool = false,
a14_lo: bool = false,
a14_hi: bool = false,
a15_lo: bool = false,
a15_hi: bool = false,
a16_lo: bool = false,
a16_hi: bool = false,
a17_lo: bool = false,
a17_hi: bool = false,
a18_lo: bool = false,
a18_hi: bool = false,
a19_lo: bool = false,
a19_hi: bool = false,
a20_lo: bool = false,
a20_hi: bool = false,
a21_lo: bool = false,
a21_hi: bool = false,
a22_lo: bool = false,
a22_hi: bool = false,
a23_lo: bool = false,
a23_hi: bool = false,
a24_lo: bool = false,
a24_hi: bool = false,
a25_lo: bool = false,
a25_hi: bool = false,
a26_lo: bool = false,
a26_hi: bool = false,
a27_lo: bool = false,
a27_hi: bool = false,
a28_lo: bool = false,
a28_hi: bool = false,
a29_lo: bool = false,
a29_hi: bool = false,
a30_lo: bool = false,
a30_hi: bool = false,
a31_lo: bool = false,
a31_hi: bool = false,
a32_lo: bool = false,
a32_hi: bool = false,
a33_lo: bool = false,
a33_hi: bool = false,
a34_lo: bool = false,
a34_hi: bool = false,
a35_lo: bool = false,
a35_hi: bool = false,
a36_lo: bool = false,
a36_hi: bool = false,
a37_lo: bool = false,
a37_hi: bool = false,
a38_lo: bool = false,
a38_hi: bool = false,
a39_lo: bool = false,
a39_hi: bool = false,
a40_lo: bool = false,
a40_hi: bool = false,
a41_lo: bool = false,
a41_hi: bool = false,
a42_lo: bool = false,
a42_hi: bool = false,
a43_lo: bool = false,
a43_hi: bool = false,
a44_lo: bool = false,
a44_hi: bool = false,
a45_lo: bool = false,
a45_hi: bool = false,
a46_lo: bool = false,
a46_hi: bool = false,
a47_lo: bool = false,
a47_hi: bool = false,
a48_lo: bool = false,
a48_hi: bool = false,
a49_lo: bool = false,
a49_hi: bool = false,
a50_lo: bool = false,
a50_hi: bool = false,
a51_lo: bool = false,
a51_hi: bool = false,
a52_lo: bool = false,
a52_hi: bool = false,
a53_lo: bool = false,
a53_hi: bool = false,
a54_lo: bool = false,
a54_hi: bool = false,
a55_lo: bool = false,
a55_hi: bool = false,
a56_lo: bool = false,
a56_hi: bool = false,
a57_lo: bool = false,
a57_hi: bool = false,
a58_lo: bool = false,
a58_hi: bool = false,
a59_lo: bool = false,
a59_hi: bool = false,
a60_lo: bool = false,
a60_hi: bool = false,
a61_lo: bool = false,
a61_hi: bool = false,
a62_lo: bool = false,
a62_hi: bool = false,
a63_lo: bool = false,
a63_hi: bool = false,
a0_x: bool = false,
a0_y: bool = false,
a0_z: bool = false,
a0_t: bool = false,
a1_x: bool = false,
a1_y: bool = false,
a1_z: bool = false,
a1_t: bool = false,
a2_x: bool = false,
a2_y: bool = false,
a2_z: bool = false,
a2_t: bool = false,
a3_x: bool = false,
a3_y: bool = false,
a3_z: bool = false,
a3_t: bool = false,
a4_x: bool = false,
a4_y: bool = false,
a4_z: bool = false,
a4_t: bool = false,
a5_x: bool = false,
a5_y: bool = false,
a5_z: bool = false,
a5_t: bool = false,
a6_x: bool = false,
a6_y: bool = false,
a6_z: bool = false,
a6_t: bool = false,
a7_x: bool = false,
a7_y: bool = false,
a7_z: bool = false,
a7_t: bool = false,
a8_x: bool = false,
a8_y: bool = false,
a8_z: bool = false,
a8_t: bool = false,
a9_x: bool = false,
a9_y: bool = false,
a9_z: bool = false,
a9_t: bool = false,
a10_x: bool = false,
a10_y: bool = false,
a10_z: bool = false,
a10_t: bool = false,
a11_x: bool = false,
a11_y: bool = false,
a11_z: bool = false,
a11_t: bool = false,
a12_x: bool = false,
a12_y: bool = false,
a12_z: bool = false,
a12_t: bool = false,
a13_x: bool = false,
a13_y: bool = false,
a13_z: bool = false,
a13_t: bool = false,
a14_x: bool = false,
a14_y: bool = false,
a14_z: bool = false,
a14_t: bool = false,
a15_x: bool = false,
a15_y: bool = false,
a15_z: bool = false,
a15_t: bool = false,
a16_x: bool = false,
a16_y: bool = false,
a16_z: bool = false,
a16_t: bool = false,
a17_x: bool = false,
a17_y: bool = false,
a17_z: bool = false,
a17_t: bool = false,
a18_x: bool = false,
a18_y: bool = false,
a18_z: bool = false,
a18_t: bool = false,
a19_x: bool = false,
a19_y: bool = false,
a19_z: bool = false,
a19_t: bool = false,
a20_x: bool = false,
a20_y: bool = false,
a20_z: bool = false,
a20_t: bool = false,
a21_x: bool = false,
a21_y: bool = false,
a21_z: bool = false,
a21_t: bool = false,
a22_x: bool = false,
a22_y: bool = false,
a22_z: bool = false,
a22_t: bool = false,
a23_x: bool = false,
a23_y: bool = false,
a23_z: bool = false,
a23_t: bool = false,
a24_x: bool = false,
a24_y: bool = false,
a24_z: bool = false,
a24_t: bool = false,
a25_x: bool = false,
a25_y: bool = false,
a25_z: bool = false,
a25_t: bool = false,
a26_x: bool = false,
a26_y: bool = false,
a26_z: bool = false,
a26_t: bool = false,
a27_x: bool = false,
a27_y: bool = false,
a27_z: bool = false,
a27_t: bool = false,
a28_x: bool = false,
a28_y: bool = false,
a28_z: bool = false,
a28_t: bool = false,
a29_x: bool = false,
a29_y: bool = false,
a29_z: bool = false,
a29_t: bool = false,
a30_x: bool = false,
a30_y: bool = false,
a30_z: bool = false,
a30_t: bool = false,
a31_x: bool = false,
a31_y: bool = false,
a31_z: bool = false,
a31_t: bool = false,
a32_x: bool = false,
a32_y: bool = false,
a32_z: bool = false,
a32_t: bool = false,
a33_x: bool = false,
a33_y: bool = false,
a33_z: bool = false,
a33_t: bool = false,
a34_x: bool = false,
a34_y: bool = false,
a34_z: bool = false,
a34_t: bool = false,
a35_x: bool = false,
a35_y: bool = false,
a35_z: bool = false,
a35_t: bool = false,
a36_x: bool = false,
a36_y: bool = false,
a36_z: bool = false,
a36_t: bool = false,
a37_x: bool = false,
a37_y: bool = false,
a37_z: bool = false,
a37_t: bool = false,
a38_x: bool = false,
a38_y: bool = false,
a38_z: bool = false,
a38_t: bool = false,
a39_x: bool = false,
a39_y: bool = false,
a39_z: bool = false,
a39_t: bool = false,
a40_x: bool = false,
a40_y: bool = false,
a40_z: bool = false,
a40_t: bool = false,
a41_x: bool = false,
a41_y: bool = false,
a41_z: bool = false,
a41_t: bool = false,
a42_x: bool = false,
a42_y: bool = false,
a42_z: bool = false,
a42_t: bool = false,
a43_x: bool = false,
a43_y: bool = false,
a43_z: bool = false,
a43_t: bool = false,
a44_x: bool = false,
a44_y: bool = false,
a44_z: bool = false,
a44_t: bool = false,
a45_x: bool = false,
a45_y: bool = false,
a45_z: bool = false,
a45_t: bool = false,
a46_x: bool = false,
a46_y: bool = false,
a46_z: bool = false,
a46_t: bool = false,
a47_x: bool = false,
a47_y: bool = false,
a47_z: bool = false,
a47_t: bool = false,
a48_x: bool = false,
a48_y: bool = false,
a48_z: bool = false,
a48_t: bool = false,
a49_x: bool = false,
a49_y: bool = false,
a49_z: bool = false,
a49_t: bool = false,
a50_x: bool = false,
a50_y: bool = false,
a50_z: bool = false,
a50_t: bool = false,
a51_x: bool = false,
a51_y: bool = false,
a51_z: bool = false,
a51_t: bool = false,
a52_x: bool = false,
a52_y: bool = false,
a52_z: bool = false,
a52_t: bool = false,
a53_x: bool = false,
a53_y: bool = false,
a53_z: bool = false,
a53_t: bool = false,
a54_x: bool = false,
a54_y: bool = false,
a54_z: bool = false,
a54_t: bool = false,
a55_x: bool = false,
a55_y: bool = false,
a55_z: bool = false,
a55_t: bool = false,
a56_x: bool = false,
a56_y: bool = false,
a56_z: bool = false,
a56_t: bool = false,
a57_x: bool = false,
a57_y: bool = false,
a57_z: bool = false,
a57_t: bool = false,
a58_x: bool = false,
a58_y: bool = false,
a58_z: bool = false,
a58_t: bool = false,
a59_x: bool = false,
a59_y: bool = false,
a59_z: bool = false,
a59_t: bool = false,
a60_x: bool = false,
a60_y: bool = false,
a60_z: bool = false,
a60_t: bool = false,
a61_x: bool = false,
a61_y: bool = false,
a61_z: bool = false,
a61_t: bool = false,
a62_x: bool = false,
a62_y: bool = false,
a62_z: bool = false,
a62_t: bool = false,
a63_x: bool = false,
a63_y: bool = false,
a63_z: bool = false,
a63_t: bool = false,
},
.lanai => packed struct {
/// Whether the inline assembly code may perform stores to memory
/// addresses other than those derived from input pointer provenance.

3
lib/std/debug/Dwarf.zig
View File

@ -1434,6 +1434,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
.arm, .armeb, .thumb, .thumbeb => 15,
.csky => 64,
.hexagon => 76,
.kvx => 64,
.lanai => 2,
.loongarch32, .loongarch64 => 64,
.m68k => 26,
@ -1457,6 +1458,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
.arm, .armeb, .thumb, .thumbeb => 11,
.csky => 14,
.hexagon => 30,
.kvx => 14,
.lanai => 5,
.loongarch32, .loongarch64 => 22,
.m68k => 14,
@ -1480,6 +1482,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
.arm, .armeb, .thumb, .thumbeb => 13,
.csky => 14,
.hexagon => 29,
.kvx => 12,
.lanai => 4,
.loongarch32, .loongarch64 => 3,
.m68k => 15,

66
lib/std/debug/cpu_context.zig
View File

@ -9,6 +9,7 @@ else switch (native_arch) {
.arm, .armeb, .thumb, .thumbeb => Arm,
.csky => Csky,
.hexagon => Hexagon,
.kvx => Kvx,
.lanai => Lanai,
.loongarch32, .loongarch64 => LoongArch,
.m68k => M68k,
@ -493,6 +494,71 @@ const Hexagon = extern struct {
}
};
/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
const Kvx = extern struct {
r: [64]u64,
ra: u64,
pc: u64,
pub inline fn current() Kvx {
var ctx: Kvx = undefined;
asm volatile (
\\ so (0)[$r32] = $r0r1r2r3
\\ ;;
\\ so (32)[$r32] = $r4r5r6r7
\\ ;;
\\ so (64)[$r32] = $r8r9r10r11
\\ ;;
\\ so (96)[$r32] = $r12r13r14r15
\\ ;;
\\ so (128)[$r32] = $r16r17r18r19
\\ ;;
\\ so (160)[$r32] = $r20r21r22r23
\\ ;;
\\ so (192)[$r32] = $r24r25r26r27
\\ ;;
\\ so (224)[$r32] = $r28r29r30r31
\\ ;;
\\ so (256)[$r32] = $r32r33r34r35
\\ ;;
\\ so (288)[$r32] = $r36r37r38r39
\\ ;;
\\ so (320)[$r32] = $r40r41r42r43
\\ ;;
\\ so (352)[$r32] = $r44r45r46r47
\\ ;;
\\ so (384)[$r32] = $r48r49r50r51
\\ ;;
\\ so (416)[$r32] = $r52r53r54r55
\\ ;;
\\ so (448)[$r32] = $r56r57r58r59
\\ get $r34 = $pc
\\ ;;
\\ so (480)[$r32] = $r60r61r62r63
\\ get $r35 = $ra
\\ ;;
\\ sq (512)[$r32] = $r34r35
:
: [ctx] "{r32}" (&ctx),
: .{ .r34 = true, .r35 = true, .memory = true });
return ctx;
}
pub fn dwarfRegisterBytes(ctx: *Kvx, register_num: u16) DwarfRegisterError![]u8 {
switch (register_num) {
0...63 => return @ptrCast(&ctx.r[register_num]),
64 => return @ptrCast(&ctx.pc),
67 => return @ptrCast(&ctx.ra),
65...66 => return error.UnsupportedRegister, // SFRs
68...255 => return error.UnsupportedRegister, // SFRs
256...767 => return error.UnsupportedRegister, // XCRs
else => return error.InvalidRegister,
}
}
};
/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
const Lanai = extern struct {
r: [32]u32,

8
lib/std/pie.zig
View File

@ -11,6 +11,7 @@ const R_ARM_RELATIVE = 23;
const R_AARCH64_RELATIVE = 1027;
const R_CSKY_RELATIVE = 9;
const R_HEXAGON_RELATIVE = 35;
const R_KVX_RELATIVE = 39;
const R_LARCH_RELATIVE = 3;
const R_68K_RELATIVE = 22;
const R_MICROBLAZE_REL = 16;
@ -31,6 +32,7 @@ const R_RELATIVE = switch (builtin.cpu.arch) {
.alpha => R_ALPHA_RELATIVE,
.csky => R_CSKY_RELATIVE,
.hexagon => R_HEXAGON_RELATIVE,
.kvx => R_KVX_RELATIVE,
.loongarch32, .loongarch64 => R_LARCH_RELATIVE,
.m68k => R_68K_RELATIVE,
.microblaze, .microblazeel => R_MICROBLAZE_REL,
@ -118,6 +120,12 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
: [ret] "=r" (-> [*]const elf.Dyn),
:
: .{ .r1 = true }),
.kvx => asm volatile (
\\ .weak _DYNAMIC
\\ .hidden _DYNAMIC
\\ pcrel %[ret] = @pcrel(_DYNAMIC)
: [ret] "=r" (-> [*]const elf.Dyn),
),
.loongarch32, .loongarch64 => asm volatile (
\\ .weak _DYNAMIC
\\ .hidden _DYNAMIC

2
lib/std/simd.zig
View File

@ -68,6 +68,8 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
if (cpu.has(.s390x, .vector)) break :blk 128;
} else if (cpu.arch.isSPARC()) {
if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64;
} else if (cpu.arch == .kvx) {
break :blk 1024;
} else if (cpu.arch == .ve) {
if (cpu.has(.ve, .vpu)) break :blk 2048;
} else if (cpu.arch.isWasm()) {

10
lib/std/start.zig
View File

@ -205,6 +205,7 @@ fn _start() callconv(.naked) noreturn {
.arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891
.csky => ".cfi_undefined lr",
.hexagon => ".cfi_undefined r31",
.kvx => ".cfi_undefined r14",
.loongarch32, .loongarch64 => ".cfi_undefined 1",
.m68k => ".cfi_undefined %%pc",
.microblaze, .microblazeel => ".cfi_undefined r15",
@ -318,6 +319,15 @@ fn _start() callconv(.naked) noreturn {
\\ r29 = add(r29, #-8)
\\ call %[posixCallMainAndExit]
,
.kvx =>
\\ make $fp = 0
\\ ;;
\\ set $ra = $fp
\\ copyd $r0 = $sp
\\ andd $sp = $sp, -32
\\ ;;
\\ goto %[posixCallMainAndExit]
,
.loongarch32, .loongarch64 =>
\\ move $fp, $zero
\\ move $ra, $zero

6
lib/zig.h
View File

@ -28,6 +28,8 @@
#define zig_arm
#elif defined(__hexagon__)
#define zig_hexagon
#elif defined(__kvx__)
#define zig_kvx
#elif defined(__loongarch32)
#define zig_loongarch32
#define zig_loongarch
@ -383,7 +385,7 @@
#define zig_trap() __asm__ volatile("udf #0xfdee")
#elif defined(zig_hexagon)
#define zig_trap() __asm__ volatile("r27:26 = memd(#0xbadc0fee)")
#elif defined(zig_loongarch) || defined(zig_powerpc)
#elif defined(zig_kvx) || defined(zig_loongarch) || defined(zig_powerpc)
#define zig_trap() __asm__ volatile(".word 0x0")
#elif defined(zig_mips)
#define zig_trap() __asm__ volatile(".word 0x3d")
@ -419,7 +421,7 @@
#define zig_breakpoint() __asm__ volatile("brk #0xf000")
#elif defined(zig_hexagon)
#define zig_breakpoint() __asm__ volatile("brkpt")
#elif defined(zig_loongarch)
#elif defined(zig_kvx) || defined(zig_loongarch)
#define zig_breakpoint() __asm__ volatile("break 0x0")
#elif defined(zig_mips)
#define zig_breakpoint() __asm__ volatile("break")

2
src/Sema.zig
View File

@ -9091,6 +9091,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
.hexagon_sysv_hvx,
.hppa_elf,
.hppa64_elf,
.kvx_lp64,
.kvx_ilp32,
.lanai_sysv,
.loongarch64_lp64,
.loongarch32_ilp32,

5
src/codegen/c.zig
View File

@ -5781,8 +5781,9 @@ fn airAsm(f: *Function, inst: Air.Inst.Index) !CValue {
c_name_buf[0] = '$';
break :name c_name;
} else if ((target.cpu.arch.isMIPS() and (mem.startsWith(u8, field_name, "fcc") or field_name[0] == 'w')) or
((target.cpu.arch.isMIPS() or target.cpu.arch == .alpha) and field_name[0] == 'f')) name: {
// "$" prefix for FCC, W and F registers
((target.cpu.arch.isMIPS() or target.cpu.arch == .alpha) and field_name[0] == 'f') or
(target.cpu.arch == .kvx and !mem.eql(u8, field_name, "memory"))) name: {
// "$" prefix for these registers
c_name_buf[0] = '$';
@memcpy((&c_name_buf)[1..][0..field_name.len], field_name);
break :name (&c_name_buf)[0 .. 1 + field_name.len];

5
src/codegen/llvm.zig
View File

@ -111,6 +111,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
.hppa,
.hppa64,
.kalimba,
.kvx,
.microblaze,
.microblazeel,
.or1k,
@ -477,6 +478,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
.hppa,
.hppa64,
.kalimba,
.kvx,
.microblaze,
.microblazeel,
.or1k,
@ -11931,6 +11933,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
.hexagon_sysv_hvx,
.hppa_elf,
.hppa64_elf,
.kvx_lp64,
.kvx_ilp32,
.lanai_sysv,
.loongarch64_lp64,
.loongarch32_ilp32,
@ -13114,6 +13118,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
.hppa,
.hppa64,
.kalimba,
.kvx,
.microblaze,
.microblazeel,
.or1k,

2
src/target.zig
View File

@ -219,6 +219,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
.hppa,
.hppa64,
.kalimba,
.kvx,
.microblaze,
.microblazeel,
.or1k,
@ -755,6 +756,7 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
=> .@"4",
.bpfeb,
.bpfel,
.kvx,
.mips64,
.mips64el,
=> .@"8",

37
tools/update_cpu_features.zig
View File

@ -973,6 +973,43 @@ const targets = [_]ArchTarget{
.td_name = "Hexagon",
},
},
.{
.zig_name = "kvx",
.llvm = null,
.extra_features = &.{
.{
.zig_name = "v3_1",
.desc = "Enable ISA v3.1",
.deps = &.{},
},
.{
.zig_name = "v3_2",
.desc = "Enable ISA v3.2",
.deps = &.{"v3_1"},
},
.{
.zig_name = "v4_1",
.desc = "Enable ISA v4.1",
.deps = &.{"v3_2"},
},
},
.extra_cpus = &.{
.{
.llvm_name = null,
.zig_name = "coolidge_v1",
.features = &.{
"v3_1",
},
},
.{
.llvm_name = null,
.zig_name = "coolidge_v2",
.features = &.{
"v3_2",
},
},
},
},
.{
.zig_name = "lanai",
.llvm = .{