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stage2 ARM: Add push, pop alias instructions; non-leaf functions
Non-leaf functions now work. Combined with simple parameters and return types, this allows more complicated programs than Hello World to be correctly compiled.
This commit is contained in:
joachimschmidt557
parent
35b228630c
commit
cfe486e388
@ -576,7 +576,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// push {fp, lr}
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// mov fp, sp
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// sub sp, sp, #reloc
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// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .fp, Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.push(.al, .{ .fp, .lr }).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .fp, Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none)).toU32());
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// TODO: prepare stack for local variables
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// const backpatch_reloc = try self.code.addManyAsArray(4);
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try self.dbgSetPrologueEnd();
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@ -592,7 +594,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// mov sp, fp
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// pop {fp, pc}
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
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// TODO: return by jumping to this code, use relocations
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// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
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// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.pop(.al, .{ .fp, .pc }).toU32());
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} else {
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try self.dbgSetPrologueEnd();
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try self.genBody(self.mod_fn.analysis.success);
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@ -1661,7 +1665,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.zero, 0, .ra).toU32());
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},
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.arm => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.pop(.al, .{ .fp, .pc }).toU32());
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// TODO: jump to the end with relocation
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// // Just add space for an instruction, patch this later
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// try self.code.resize(self.code.items.len + 4);
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// try self.exitlude_jump_relocs.append(self.gpa, self.code.items.len - 4);
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@ -2316,7 +2322,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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try self.genSetReg(src, reg, .{ .immediate = addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, Instruction.Offset.none).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, .{ .offset = Instruction.Offset.none }).toU32());
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},
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else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
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},
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@ -417,10 +417,10 @@ pub const Instruction = union(enum) {
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rd: Register,
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rn: Register,
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offset: Offset,
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pre_post: u1,
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up_down: u1,
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pre_index: bool,
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positive: bool,
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byte_word: u1,
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write_back: u1,
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write_back: bool,
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load_store: u1,
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) Instruction {
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return Instruction{
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@ -430,10 +430,10 @@ pub const Instruction = union(enum) {
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.rd = rd.id(),
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.offset = offset.toU12(),
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.load_store = load_store,
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.write_back = write_back,
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.write_back = if (write_back) 1 else 0,
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.byte_word = byte_word,
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.up_down = up_down,
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.pre_post = pre_post,
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.up_down = if (positive) 1 else 0,
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.pre_post = if (pre_index) 1 else 0,
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.imm = if (offset == .Immediate) 0 else 1,
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},
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};
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@ -626,20 +626,27 @@ pub const Instruction = union(enum) {
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// Single data transfer
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pub fn ldr(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
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return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 1);
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pub const OffsetArgs = struct {
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pre_index: bool = true,
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positive: bool = true,
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offset: Offset,
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write_back: bool = false,
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};
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pub fn ldr(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
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return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 0, args.write_back, 1);
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}
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pub fn ldrb(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
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return singleDataTransfer(cond, rd, rn, offset, 1, 1, 1, 0, 1);
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pub fn ldrb(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
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return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 1);
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}
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pub fn str(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
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return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 0);
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pub fn str(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
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return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 0, args.write_back, 0);
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}
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pub fn strb(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
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return singleDataTransfer(cond, rd, rn, offset, 1, 1, 1, 0, 0);
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pub fn strb(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
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return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 0);
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}
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// Block data transfer
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@ -721,6 +728,58 @@ pub const Instruction = union(enum) {
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pub fn bkpt(imm: u16) Instruction {
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return breakpoint(imm);
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}
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// Aliases
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pub fn pop(cond: Condition, args: anytype) Instruction {
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if (@typeInfo(@TypeOf(args)) != .Struct) {
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@compileError("Expected tuple or struct argument, found " ++ @typeName(@TypeOf(args)));
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}
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if (args.len < 1) {
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@compileError("Expected at least one register");
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} else if (args.len == 1) {
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const reg = args[0];
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return ldr(cond, reg, .sp, .{
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.pre_index = false,
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.positive = true,
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.offset = Offset.imm(4),
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.write_back = false,
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});
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} else {
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var register_list: u16 = 0;
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inline for (args) |arg| {
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const reg = @as(Register, arg);
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register_list |= @as(u16, 1) << reg.id();
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}
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return ldm(cond, .sp, true, @bitCast(RegisterList, register_list));
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}
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}
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pub fn push(cond: Condition, args: anytype) Instruction {
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if (@typeInfo(@TypeOf(args)) != .Struct) {
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@compileError("Expected tuple or struct argument, found " ++ @typeName(@TypeOf(args)));
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}
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if (args.len < 1) {
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@compileError("Expected at least one register");
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} else if (args.len == 1) {
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const reg = args[0];
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return str(cond, reg, .sp, .{
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.pre_index = true,
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.positive = false,
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.offset = Offset.imm(4),
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.write_back = true,
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});
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} else {
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var register_list: u16 = 0;
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inline for (args) |arg| {
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const reg = @as(Register, arg);
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register_list |= @as(u16, 1) << reg.id();
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}
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return stmdb(cond, .sp, true, @bitCast(RegisterList, register_list));
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}
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}
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};
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test "serialize instructions" {
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@ -747,11 +806,15 @@ test "serialize instructions" {
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.expected = 0b1110_00010_0_001111_0101_000000000000,
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},
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.{ // ldr r0, [r2, #42]
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.inst = Instruction.ldr(.al, .r0, .r2, Instruction.Offset.imm(42)),
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.inst = Instruction.ldr(.al, .r0, .r2, .{
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.offset = Instruction.Offset.imm(42),
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}),
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.expected = 0b1110_01_0_1_1_0_0_1_0010_0000_000000101010,
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},
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.{ // str r0, [r3]
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.inst = Instruction.str(.al, .r0, .r3, Instruction.Offset.none),
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.inst = Instruction.str(.al, .r0, .r3, .{
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.offset = Instruction.Offset.none,
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}),
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.expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
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},
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.{ // b #12
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@ -789,3 +852,43 @@ test "serialize instructions" {
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testing.expectEqual(case.expected, actual);
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}
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}
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test "aliases" {
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const Testcase = struct {
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expected: Instruction,
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actual: Instruction,
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};
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const testcases = [_]Testcase{
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.{ // pop { r6 }
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.actual = Instruction.pop(.al, .{.r6}),
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.expected = Instruction.ldr(.al, .r6, .sp, .{
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.pre_index = false,
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.positive = true,
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.offset = Instruction.Offset.imm(4),
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.write_back = false,
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}),
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},
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.{ // pop { r1, r5 }
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.actual = Instruction.pop(.al, .{ .r1, .r5 }),
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.expected = Instruction.ldm(.al, .sp, true, .{ .r1 = true, .r5 = true }),
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},
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.{ // push { r3 }
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.actual = Instruction.push(.al, .{.r3}),
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.expected = Instruction.str(.al, .r3, .sp, .{
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.pre_index = true,
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.positive = false,
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.offset = Instruction.Offset.imm(4),
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.write_back = true,
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}),
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},
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.{ // push { r0, r2 }
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.actual = Instruction.push(.al, .{ .r0, .r2 }),
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.expected = Instruction.stmdb(.al, .sp, true, .{ .r0 = true, .r2 = true }),
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},
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};
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for (testcases) |case| {
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testing.expectEqual(case.expected.toU32(), case.actual.toU32());
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}
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}
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