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Zcu: simplify atomicPtrAlignment()

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The value being computed here is almost always equal to the pointer bit width.
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Alex Rønne Petersen 2025-10-19 22:46:36 +02:00
parent ae789fa50a
commit cd56b06352
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1 changed files with 7 additions and 51 deletions
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src/Zcu.zig
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@ -3836,61 +3836,17 @@ pub fn atomicPtrAlignment(
) AtomicPtrAlignmentError!Alignment {
const target = zcu.getTarget();
const max_atomic_bits: u16 = switch (target.cpu.arch) {
.avr,
.msp430,
=> 16,
.arc,
.arm,
.armeb,
.hexagon,
.m68k,
.mips,
.mipsel,
.nvptx,
.or1k,
.powerpc,
.powerpcle,
.riscv32,
.riscv32be,
.sparc,
.thumb,
.thumbeb,
.x86,
.xcore,
.kalimba,
.lanai,
.wasm32,
.csky,
.spirv32,
.loongarch32,
.xtensa,
.propeller,
=> 32,
.amdgcn,
.bpfel,
.bpfeb,
.mips64,
.mips64el,
.nvptx64,
.powerpc64,
.powerpc64le,
.riscv64,
.riscv64be,
.sparc64,
.s390x,
.wasm64,
.ve,
.spirv64,
.loongarch64,
=> 64,
.aarch64,
.aarch64_be,
=> 128,
.x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64,
.mips64,
.mips64el,
=> 64, // N32 should be 64, not 32.
.x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64, // x32 should be 64 or 128, not 32.
else => target.ptrBitWidth(),
};
if (ty.toIntern() == .bool_type) return .none;