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https://github.com/ziglang/zig.git
synced 2026-02-21 00:35:10 +00:00
x86_64: implement some float and float vector movement
This allows actually storing value of these supported types in registers, and not restricting them to stack slots.
This commit is contained in:
Jacob Young
parent
3a5e3c52e0
commit
cba195c117
@ -2008,6 +2008,11 @@ fn computeFrameLayout(self: *Self) !FrameLayout {
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};
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}
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fn getFrameAddrAlignment(self: *Self, frame_addr: FrameAddr) u32 {
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const alloc_align = @as(u32, 1) << self.frame_allocs.get(@enumToInt(frame_addr.index)).abi_align;
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return @min(alloc_align, @bitCast(u32, frame_addr.off) & (alloc_align - 1));
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}
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fn allocFrameIndex(self: *Self, alloc: FrameAlloc) !FrameIndex {
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const frame_allocs_slice = self.frame_allocs.slice();
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const frame_size = frame_allocs_slice.items(.abi_size);
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@ -2051,24 +2056,36 @@ fn allocTempRegOrMem(self: *Self, elem_ty: Type, reg_ok: bool) !MCValue {
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return self.allocRegOrMemAdvanced(elem_ty, null, reg_ok);
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}
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fn allocRegOrMemAdvanced(self: *Self, elem_ty: Type, inst: ?Air.Inst.Index, reg_ok: bool) !MCValue {
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const abi_size = math.cast(u32, elem_ty.abiSize(self.target.*)) orelse {
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fn allocRegOrMemAdvanced(self: *Self, ty: Type, inst: ?Air.Inst.Index, reg_ok: bool) !MCValue {
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const abi_size = math.cast(u32, ty.abiSize(self.target.*)) orelse {
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const mod = self.bin_file.options.module.?;
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return self.fail("type '{}' too big to fit into stack frame", .{elem_ty.fmt(mod)});
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return self.fail("type '{}' too big to fit into stack frame", .{ty.fmt(mod)});
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};
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if (reg_ok) {
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// Make sure the type can fit in a register before we try to allocate one.
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
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const ptr_bytes: u64 = @divExact(ptr_bits, 8);
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if (abi_size <= ptr_bytes) {
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if (self.register_manager.tryAllocReg(inst, regClassForType(elem_ty))) |reg| {
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if (reg_ok) need_mem: {
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if (abi_size <= @as(u32, switch (ty.zigTypeTag()) {
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.Float => switch (ty.floatBits(self.target.*)) {
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16, 32, 64, 128 => 16,
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80 => break :need_mem,
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else => unreachable,
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},
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.Vector => switch (ty.childType().zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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16, 32, 64 => if (self.hasFeature(.avx)) 32 else 16,
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80, 128 => break :need_mem,
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else => unreachable,
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},
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else => break :need_mem,
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},
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else => 8,
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})) {
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if (self.register_manager.tryAllocReg(inst, regClassForType(ty))) |reg| {
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return MCValue{ .register = registerAlias(reg, abi_size) };
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}
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}
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}
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const frame_index = try self.allocFrameIndex(FrameAlloc.initType(elem_ty, self.target.*));
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const frame_index = try self.allocFrameIndex(FrameAlloc.initType(ty, self.target.*));
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return .{ .load_frame = .{ .index = frame_index } };
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}
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@ -4442,12 +4459,19 @@ fn airRound(self: *Self, inst: Air.Inst.Index, mode: Immediate) !void {
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}),
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};
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assert(dst_mcv.isRegister());
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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const dst_reg = registerAlias(dst_mcv.getReg().?, abi_size);
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if (src_mcv.isRegister())
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try self.asmRegisterRegisterImmediate(mir_tag, dst_mcv.getReg().?, src_mcv.getReg().?, mode)
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try self.asmRegisterRegisterImmediate(
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mir_tag,
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dst_reg,
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registerAlias(src_mcv.getReg().?, abi_size),
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mode,
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)
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else
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try self.asmRegisterMemoryImmediate(
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mir_tag,
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dst_mcv.getReg().?,
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dst_reg,
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src_mcv.mem(Memory.PtrSize.fromSize(@intCast(u32, ty.abiSize(self.target.*)))),
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mode,
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);
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@ -7847,19 +7871,43 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAirResult(inst, result);
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}
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fn movMirTag(self: *Self, ty: Type) !Mir.Inst.Tag {
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return switch (ty.zigTypeTag()) {
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else => .mov,
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fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.Tag {
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switch (ty.zigTypeTag()) {
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else => return .mov,
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.Float => switch (ty.floatBits(self.target.*)) {
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16 => unreachable, // needs special handling
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32 => .movss,
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64 => .movsd,
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128 => .movaps,
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else => return self.fail("TODO movMirTag from {}", .{
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ty.fmt(self.bin_file.options.module.?),
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}),
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32 => return if (self.hasFeature(.avx)) .vmovss else .movss,
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64 => return if (self.hasFeature(.avx)) .vmovsd else .movsd,
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128 => return if (self.hasFeature(.avx))
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if (aligned) .vmovaps else .vmovups
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else if (aligned) .movaps else .movups,
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else => {},
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},
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};
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.Vector => switch (ty.childType().zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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16 => unreachable, // needs special handling
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32 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx)) .vmovss else .movss,
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2...4 => return if (self.hasFeature(.avx))
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if (aligned) .vmovaps else .vmovups
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else if (aligned) .movaps else .movups,
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5...8 => if (self.hasFeature(.avx)) return if (aligned) .vmovaps else .vmovups,
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else => {},
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},
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64 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx)) .vmovsd else .movsd,
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2 => return if (self.hasFeature(.avx))
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if (aligned) .vmovaps else .vmovups
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else if (aligned) .movaps else .movups,
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3...4 => if (self.hasFeature(.avx)) return if (aligned) .vmovaps else .vmovups,
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else => {},
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},
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else => {},
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},
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else => {},
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},
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}
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return self.fail("TODO movMirTag for {}", .{ty.fmt(self.bin_file.options.module.?)});
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}
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fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError!void {
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@ -8016,7 +8064,11 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
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0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }),
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else => .lea,
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},
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.indirect, .load_frame => try self.movMirTag(ty),
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.indirect => try self.movMirTag(ty, false),
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.load_frame => |frame_addr| try self.movMirTag(
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ty,
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self.getFrameAddrAlignment(frame_addr) >= ty.abiAlignment(self.target.*),
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),
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.lea_frame => .lea,
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else => unreachable,
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},
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@ -8040,7 +8092,11 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
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)
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else
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self.asmRegisterMemory(
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try self.movMirTag(ty),
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try self.movMirTag(ty, mem.isAlignedGeneric(
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u32,
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@bitCast(u32, small_addr),
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ty.abiAlignment(self.target.*),
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)),
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registerAlias(dst_reg, abi_size),
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src_mem,
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);
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@ -8080,7 +8136,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
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)
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else
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try self.asmRegisterMemory(
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try self.movMirTag(ty),
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try self.movMirTag(ty, false),
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registerAlias(dst_reg, abi_size),
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src_mem,
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);
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@ -8194,7 +8250,24 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
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)
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else
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try self.asmMemoryRegister(
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try self.movMirTag(ty),
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try self.movMirTag(ty, switch (base) {
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.none => mem.isAlignedGeneric(
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u32,
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@bitCast(u32, disp),
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ty.abiAlignment(self.target.*),
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),
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.reg => |reg| switch (reg) {
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.es, .cs, .ss, .ds => mem.isAlignedGeneric(
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u32,
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@bitCast(u32, disp),
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ty.abiAlignment(self.target.*),
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),
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else => false,
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},
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.frame => |frame_index| self.getFrameAddrAlignment(
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.{ .index = frame_index, .off = disp },
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) >= ty.abiAlignment(self.target.*),
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}),
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dst_mem,
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registerAlias(src_reg, abi_size),
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);
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@ -8415,7 +8488,7 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {
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defer if (operand_lock) |lock| self.register_manager.unlockReg(lock);
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const dest = try self.allocRegOrMem(inst, true);
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try self.genCopy(self.air.typeOfIndex(inst), dest, operand);
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try self.genCopy(if (!dest.isMemory() or operand.isMemory()) dst_ty else src_ty, dest, operand);
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break :result dest;
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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@ -206,7 +206,7 @@ pub fn format(
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try writer.print("+{s} ", .{tag});
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},
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.m, .mi, .m1, .mc, .vmi => try writer.print("/{d} ", .{encoding.modRmExt()}),
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.mr, .rm, .rmi, .mri, .mrc, .rvm, .rvmi => try writer.writeAll("/r "),
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.mr, .rm, .rmi, .mri, .mrc, .rvm, .rvmi, .mvr => try writer.writeAll("/r "),
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}
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switch (encoding.data.op_en) {
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@ -230,7 +230,7 @@ pub fn format(
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};
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try writer.print("{s} ", .{tag});
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},
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.np, .fd, .td, .o, .m, .m1, .mc, .mr, .rm, .mrc, .rvm => {},
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.np, .fd, .td, .o, .m, .m1, .mc, .mr, .rm, .mrc, .rvm, .mvr => {},
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}
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try writer.print("{s} ", .{@tagName(encoding.mnemonic)});
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@ -332,7 +332,12 @@ pub const Mnemonic = enum {
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// SSE4.1
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roundsd, roundss,
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// AVX
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vmovddup, vmovshdup, vmovsldup,
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vmovapd, vmovaps,
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vmovddup,
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vmovsd,
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vmovshdup, vmovsldup,
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vmovss,
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vmovupd, vmovups,
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vpextrw, vpinsrw,
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vpshufhw, vpshuflw,
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vpsrld, vpsrlq, vpsrlw,
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@ -357,7 +362,7 @@ pub const OpEn = enum {
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fd, td,
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m1, mc, mi, mr, rm,
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rmi, mri, mrc,
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vmi, rvm, rvmi,
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vmi, rvm, rvmi, mvr,
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// zig fmt: on
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};
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@ -549,9 +554,10 @@ pub const Op = enum {
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return switch (op) {
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.rm8, .rm16, .rm32, .rm64,
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.r32_m16, .r64_m16,
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.m8, .m16, .m32, .m64, .m80, .m128,
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.m8, .m16, .m32, .m64, .m80, .m128, .m256,
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.m,
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.xmm_m32, .xmm_m64, .xmm_m128, .ymm_m256,
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.xmm_m32, .xmm_m64, .xmm_m128,
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.ymm_m256,
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=> true,
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else => false,
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};
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@ -184,9 +184,15 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct {
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.roundsd,
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.roundss,
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.vmovapd,
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.vmovaps,
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.vmovddup,
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.vmovsd,
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.vmovshdup,
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.vmovsldup,
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.vmovss,
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.vmovupd,
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.vmovups,
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.vpextrw,
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.vpinsrw,
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.vpshufhw,
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@ -282,12 +282,24 @@ pub const Inst = struct {
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/// Round scalar single-precision floating-point values
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roundss,
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/// Move aligned packed double-precision floating-point values
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vmovapd,
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/// Move aligned packed single-precision floating-point values
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vmovaps,
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/// Replicate double floating-point values
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vmovddup,
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/// Move or merge scalar double-precision floating-point value
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vmovsd,
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/// Replicate single floating-point values
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vmovshdup,
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/// Replicate single floating-point values
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vmovsldup,
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/// Move or merge scalar single-precision floating-point value
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vmovss,
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/// Move unaligned packed double-precision floating-point values
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vmovupd,
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/// Move unaligned packed single-precision floating-point values
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vmovups,
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/// Extract word
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vpextrw,
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/// Insert word
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@ -228,7 +228,7 @@ pub const Instruction = struct {
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.td => try encoder.imm64(inst.ops[0].mem.moffs.offset),
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else => {
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const mem_op = switch (data.op_en) {
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.m, .mi, .m1, .mc, .mr, .mri, .mrc => inst.ops[0],
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.m, .mi, .m1, .mc, .mr, .mri, .mrc, .mvr => inst.ops[0],
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.rm, .rmi, .vmi => inst.ops[1],
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.rvm, .rvmi => inst.ops[2],
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else => unreachable,
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@ -239,6 +239,7 @@ pub const Instruction = struct {
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.m, .mi, .m1, .mc, .vmi => enc.modRmExt(),
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.mr, .mri, .mrc => inst.ops[1].reg.lowEnc(),
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.rm, .rmi, .rvm, .rvmi => inst.ops[0].reg.lowEnc(),
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.mvr => inst.ops[2].reg.lowEnc(),
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else => unreachable,
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};
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try encoder.modRm_direct(rm, reg.lowEnc());
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@ -248,6 +249,7 @@ pub const Instruction = struct {
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.m, .mi, .m1, .mc, .vmi => .none,
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.mr, .mri, .mrc => inst.ops[1],
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.rm, .rmi, .rvm, .rvmi => inst.ops[0],
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.mvr => inst.ops[2],
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else => unreachable,
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};
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try encodeMemory(enc, mem, op, encoder);
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@ -315,7 +317,7 @@ pub const Instruction = struct {
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}
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else
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null,
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.vmi, .rvm, .rvmi => unreachable,
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.vmi, .rvm, .rvmi, .mvr => unreachable,
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};
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if (segment_override) |seg| {
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legacy.setSegmentOverride(seg);
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@ -350,7 +352,7 @@ pub const Instruction = struct {
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rex.b = b_x_op.isBaseExtended();
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rex.x = b_x_op.isIndexExtended();
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},
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.vmi, .rvm, .rvmi => unreachable,
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.vmi, .rvm, .rvmi, .mvr => unreachable,
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}
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try encoder.rex(rex);
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@ -372,10 +374,11 @@ pub const Instruction = struct {
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switch (op_en) {
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.np, .i, .zi, .fd, .td, .d => {},
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.o, .oi => vex.b = inst.ops[0].reg.isExtended(),
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.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc, .vmi, .rvm, .rvmi => {
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.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc, .vmi, .rvm, .rvmi, .mvr => {
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const r_op = switch (op_en) {
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.rm, .rmi, .rvm, .rvmi => inst.ops[0],
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.mr, .mri, .mrc => inst.ops[1],
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.mvr => inst.ops[2],
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.m, .mi, .m1, .mc, .vmi => .none,
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else => unreachable,
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};
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@ -383,7 +386,7 @@ pub const Instruction = struct {
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const b_x_op = switch (op_en) {
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.rm, .rmi, .vmi => inst.ops[1],
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.m, .mi, .m1, .mc, .mr, .mri, .mrc => inst.ops[0],
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.m, .mi, .m1, .mc, .mr, .mri, .mrc, .mvr => inst.ops[0],
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.rvm, .rvmi => inst.ops[2],
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else => unreachable,
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};
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@ -974,12 +974,42 @@ pub const table = [_]Entry{
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.{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .none, .sse4_1 },
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// AVX
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.{ .vmovapd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_128, .avx },
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.{ .vmovapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_128, .avx },
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.{ .vmovapd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_256, .avx },
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.{ .vmovapd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_256, .avx },
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.{ .vmovaps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x28 }, 0, .vex_128, .avx },
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.{ .vmovaps, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x29 }, 0, .vex_128, .avx },
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.{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256, .avx },
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.{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256, .avx },
|
||||
|
||||
.{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128, .avx },
|
||||
|
||||
.{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_128, .avx },
|
||||
.{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_128, .avx },
|
||||
.{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_128, .avx },
|
||||
.{ .vmovsd, .mr, &.{ .m64, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_128, .avx },
|
||||
|
||||
.{ .vmovshdup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_128, .avx },
|
||||
|
||||
.{ .vmovsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_128, .avx },
|
||||
|
||||
.{ .vmovss, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_128, .avx },
|
||||
.{ .vmovss, .rm, &.{ .xmm, .m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_128, .avx },
|
||||
.{ .vmovss, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_128, .avx },
|
||||
.{ .vmovss, .mr, &.{ .m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_128, .avx },
|
||||
|
||||
.{ .vmovupd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_128, .avx },
|
||||
.{ .vmovupd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_128, .avx },
|
||||
.{ .vmovupd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_256, .avx },
|
||||
.{ .vmovupd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_256, .avx },
|
||||
|
||||
.{ .vmovups, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x10 }, 0, .vex_128, .avx },
|
||||
.{ .vmovups, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x11 }, 0, .vex_128, .avx },
|
||||
.{ .vmovups, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x10 }, 0, .vex_256, .avx },
|
||||
.{ .vmovups, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x11 }, 0, .vex_256, .avx },
|
||||
|
||||
.{ .vpextrw, .mri, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128, .avx },
|
||||
.{ .vpextrw, .mri, &.{ .r64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128_long, .avx },
|
||||
.{ .vpextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128, .avx },
|
||||
|
||||
@ -399,7 +399,8 @@ fn testBinaryNot128(comptime Type: type, x: Type) !void {
|
||||
|
||||
test "division" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64 and
|
||||
!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -2,9 +2,11 @@ const std = @import("std");
|
||||
const builtin = @import("builtin");
|
||||
const expect = std.testing.expect;
|
||||
|
||||
const stage2_x86_64_without_hardware_fma_support = builtin.zig_backend == .stage2_x86_64 and
|
||||
!std.Target.x86.featureSetHas(builtin.cpu.features, .fma);
|
||||
|
||||
test "@mulAdd" {
|
||||
if (builtin.zig_backend == .stage2_x86_64 and
|
||||
!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .fma)) return error.SkipZigTest; // TODO
|
||||
if (stage2_x86_64_without_hardware_fma_support) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -118,7 +120,7 @@ fn vector32() !void {
|
||||
|
||||
test "vector f32" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (stage2_x86_64_without_hardware_fma_support) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -141,7 +143,7 @@ fn vector64() !void {
|
||||
|
||||
test "vector f64" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (stage2_x86_64_without_hardware_fma_support) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user