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- rework CFI instruction parsing to not use std.meta
- move register formatting code to zig-dwardump
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kcbanner
parent
e72e762d1e
commit
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@ -25,21 +25,6 @@ pub fn fpRegNum(reg_ctx: RegisterContext) u8 {
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.x86_64 => 6,
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.arm => 11,
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.aarch64 => 29,
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// const ctx = @ptrCast(*const os.ucontext_t, @alignCast(@alignOf(os.ucontext_t), ctx_ptr));
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// const ip = switch (native_os) {
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// .macos => @intCast(usize, ctx.mcontext.ss.pc),
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// .netbsd => @intCast(usize, ctx.mcontext.gregs[os.REG.PC]),
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// .freebsd => @intCast(usize, ctx.mcontext.gpregs.elr),
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// else => @intCast(usize, ctx.mcontext.pc),
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// };
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// // x29 is the ABI-designated frame pointer
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// const bp = switch (native_os) {
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// .macos => @intCast(usize, ctx.mcontext.ss.fp),
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// .netbsd => @intCast(usize, ctx.mcontext.gregs[os.REG.FP]),
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// .freebsd => @intCast(usize, ctx.mcontext.gpregs.x[os.REG.FP]),
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// else => @intCast(usize, ctx.mcontext.regs[29]),
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// };
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else => unreachable,
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};
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}
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@ -231,7 +216,10 @@ pub fn regBytes(ucontext_ptr: anytype, reg_number: u8, reg_ctx: ?RegisterContext
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0...29 => mem.asBytes(&ucontext_ptr.mcontext.gpregs.x[reg_number]),
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30 => mem.asBytes(&ucontext_ptr.mcontext.gpregs.lr),
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31 => mem.asBytes(&ucontext_ptr.mcontext.gpregs.sp),
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32 => mem.asBytes(&ucontext_ptr.mcontext.gpregs.elr), // TODO: This seems wrong, but it was in the old debug.zig code for PC, check this
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// TODO: This seems wrong, but it was in the previous debug.zig code for mapping PC, check this
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32 => mem.asBytes(&ucontext_ptr.mcontext.gpregs.elr),
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else => error.InvalidRegister,
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},
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else => switch (reg_number) {
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@ -252,76 +240,3 @@ pub fn getRegDefaultValue(reg_number: u8, out: []u8) void {
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_ = reg_number;
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@memset(out, undefined);
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}
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fn writeUnknownReg(writer: anytype, reg_number: u8) !void {
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try writer.print("reg{}", .{reg_number});
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}
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pub fn writeRegisterName(writer: anytype, arch: ?std.Target.Cpu.Arch, reg_number: u8) !void {
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if (arch) |a| {
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switch (a) {
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.x86_64 => {
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switch (reg_number) {
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0 => try writer.writeAll("RAX"),
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1 => try writer.writeAll("RDX"),
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2 => try writer.writeAll("RCX"),
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3 => try writer.writeAll("RBX"),
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4 => try writer.writeAll("RSI"),
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5 => try writer.writeAll("RDI"),
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6 => try writer.writeAll("RBP"),
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7 => try writer.writeAll("RSP"),
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8...15 => try writer.print("R{}", .{reg_number}),
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16 => try writer.writeAll("RIP"),
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17...32 => try writer.print("XMM{}", .{reg_number - 17}),
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33...40 => try writer.print("ST{}", .{reg_number - 33}),
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41...48 => try writer.print("MM{}", .{reg_number - 41}),
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49 => try writer.writeAll("RFLAGS"),
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50 => try writer.writeAll("ES"),
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51 => try writer.writeAll("CS"),
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52 => try writer.writeAll("SS"),
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53 => try writer.writeAll("DS"),
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54 => try writer.writeAll("FS"),
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55 => try writer.writeAll("GS"),
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// 56-57 Reserved
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58 => try writer.writeAll("FS.BASE"),
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59 => try writer.writeAll("GS.BASE"),
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// 60-61 Reserved
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62 => try writer.writeAll("TR"),
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63 => try writer.writeAll("LDTR"),
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64 => try writer.writeAll("MXCSR"),
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65 => try writer.writeAll("FCW"),
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66 => try writer.writeAll("FSW"),
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67...82 => try writer.print("XMM{}", .{reg_number - 51}),
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// 83-117 Reserved
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118...125 => try writer.print("K{}", .{reg_number - 118}),
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// 126-129 Reserved
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else => try writeUnknownReg(writer, reg_number),
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}
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},
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// TODO: Add x86, aarch64
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else => try writeUnknownReg(writer, reg_number),
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}
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} else try writeUnknownReg(writer, reg_number);
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}
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const FormatRegisterData = struct {
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reg_number: u8,
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arch: ?std.Target.Cpu.Arch,
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};
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pub fn formatRegister(
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data: FormatRegisterData,
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comptime fmt: []const u8,
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options: std.fmt.FormatOptions,
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writer: anytype,
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) !void {
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_ = fmt;
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_ = options;
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try writeRegisterName(writer, data.arch, data.reg_number);
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}
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pub fn fmtRegister(reg_number: u8, arch: ?std.Target.Cpu.Arch) std.fmt.Formatter(formatRegister) {
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return .{ .data = .{ .reg_number = reg_number, .arch = arch } };
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}
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@ -38,12 +38,12 @@ const Opcode = enum(u8) {
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val_expression = 0x16,
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// These opcodes encode an operand in the lower 6 bits of the opcode itself
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pub const lo_inline = Opcode.advance_loc;
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pub const lo_inline = @enumToInt(Opcode.advance_loc);
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pub const hi_inline = @enumToInt(Opcode.restore) | 0b111111;
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// These opcodes are trailed by zero or more operands
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pub const lo_reserved = Opcode.nop;
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pub const hi_reserved = Opcode.val_expression;
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pub const lo_reserved = @enumToInt(Opcode.nop);
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pub const hi_reserved = @enumToInt(Opcode.val_expression);
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// Vendor-specific opcodes
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pub const lo_user = 0x1c;
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@ -187,28 +187,40 @@ pub const Instruction = union(Opcode) {
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val_offset_sf: InstructionType(.{ .a = .uleb128_offset, .b = .sleb128_offset }),
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val_expression: InstructionType(.{ .a = .uleb128_offset, .block = .block }),
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fn readOperands(
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self: *Instruction,
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stream: *std.io.FixedBufferStream([]const u8),
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opcode_value: ?u6,
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addr_size_bytes: u8,
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endian: std.builtin.Endian,
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) !void {
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switch (self.*) {
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inline else => |*inst| inst.* = try @TypeOf(inst.*).read(stream, opcode_value, addr_size_bytes, endian),
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}
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}
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pub fn read(
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stream: *std.io.FixedBufferStream([]const u8),
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addr_size_bytes: u8,
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endian: std.builtin.Endian,
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) !Instruction {
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@setEvalBranchQuota(1800);
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return switch (try stream.reader().readByte()) {
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inline @enumToInt(Opcode.lo_inline)...Opcode.hi_inline => |opcode| blk: {
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inline Opcode.lo_inline...Opcode.hi_inline => |opcode| blk: {
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const e = @intToEnum(Opcode, opcode & 0b11000000);
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const payload_type = std.meta.TagPayload(Instruction, e);
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const value = try payload_type.read(stream, @intCast(u6, opcode & 0b111111), addr_size_bytes, endian);
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break :blk @unionInit(Instruction, @tagName(e), value);
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var result = @unionInit(Instruction, @tagName(e), undefined);
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try result.readOperands(stream, @intCast(u6, opcode & 0b111111), addr_size_bytes, endian);
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break :blk result;
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},
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inline @enumToInt(Opcode.lo_reserved)...@enumToInt(Opcode.hi_reserved) => |opcode| blk: {
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inline Opcode.lo_reserved...Opcode.hi_reserved => |opcode| blk: {
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const e = @intToEnum(Opcode, opcode);
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const payload_type = std.meta.TagPayload(Instruction, e);
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const value = try payload_type.read(stream, null, addr_size_bytes, endian);
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break :blk @unionInit(Instruction, @tagName(e), value);
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var result = @unionInit(Instruction, @tagName(e), undefined);
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try result.readOperands(stream, null, addr_size_bytes, endian);
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break :blk result;
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},
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Opcode.lo_user...Opcode.hi_user => error.UnimplementedUserOpcode,
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else => |opcode| blk: {
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// TODO: Remove this
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std.debug.print("Opcode {x}\n", .{opcode});
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break :blk error.InvalidOpcode;
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