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x86_64: fix large not and atomicrmw
This commit is contained in:
Jacob Young
parent
00ae3592e6
commit
c388960042
@ -2050,13 +2050,10 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
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registerAlias(src_reg, min_abi_size),
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);
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},
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.load_frame => |frame_addr| try self.asmRegisterMemory(
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.memory, .indirect, .load_frame => try self.asmRegisterMemory(
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tag,
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dst_alias,
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Memory.sib(Memory.PtrSize.fromSize(min_abi_size), .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off,
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}),
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src_mcv.mem(Memory.PtrSize.fromSize(min_abi_size)),
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),
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else => return self.fail("TODO airIntCast from {s} to {s}", .{
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@tagName(src_mcv),
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@ -2738,19 +2735,9 @@ fn genIntMulDivOpMir(
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};
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switch (mat_rhs) {
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.register => |reg| try self.asmRegister(tag, registerAlias(reg, abi_size)),
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.indirect, .load_frame => try self.asmMemory(
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.memory, .indirect, .load_frame => try self.asmMemory(
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tag,
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Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (mat_rhs) {
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.indirect => |reg_off| .{
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.base = .{ .reg = reg_off.reg },
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.disp = reg_off.off,
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},
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.load_frame => |frame_addr| .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off,
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},
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else => unreachable,
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}),
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mat_rhs.mem(Memory.PtrSize.fromSize(abi_size)),
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),
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else => unreachable,
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}
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@ -4628,9 +4615,6 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:
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if (src_ty.zigTypeTag() == .Vector) {
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return self.fail("TODO implement genUnOp for {}", .{src_ty.fmt(self.bin_file.options.module.?)});
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}
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if (src_ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genUnOp for {}", .{src_ty.fmt(self.bin_file.options.module.?)});
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}
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switch (src_mcv) {
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.eflags => |cc| switch (tag) {
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@ -4646,13 +4630,13 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:
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};
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defer if (src_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_mcv: MCValue = if (maybe_inst) |inst|
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if (self.reuseOperand(inst, src_air, 0, src_mcv))
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src_mcv
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else
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try self.copyToRegisterWithInstTracking(inst, src_ty, src_mcv)
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else
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.{ .register = try self.copyToTmpRegister(src_ty, src_mcv) };
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const dst_mcv: MCValue = dst: {
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if (maybe_inst) |inst| if (self.reuseOperand(inst, src_air, 0, src_mcv)) break :dst src_mcv;
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const dst_mcv = try self.allocRegOrMemAdvanced(src_ty, maybe_inst, true);
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try self.genCopy(src_ty, dst_mcv, src_mcv);
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break :dst dst_mcv;
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};
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const dst_lock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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@ -4661,19 +4645,33 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:
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switch (tag) {
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.not => {
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const limb_abi_size = @intCast(u16, @min(src_ty.abiSize(self.target.*), 8));
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const int_info = if (src_ty.tag() == .bool)
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std.builtin.Type.Int{ .signedness = .unsigned, .bits = 1 }
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else
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src_ty.intInfo(self.target.*);
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const extra_bits = self.regExtraBits(src_ty);
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if (int_info.signedness == .unsigned and extra_bits > 0) {
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const mask = (@as(u64, 1) << @intCast(u6, src_ty.bitSize(self.target.*))) - 1;
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try self.genBinOpMir(.xor, src_ty, dst_mcv, .{ .immediate = mask });
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} else try self.genUnOpMir(.not, src_ty, dst_mcv);
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var byte_off: i32 = 0;
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while (byte_off * 8 < int_info.bits) : (byte_off += limb_abi_size) {
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var limb_pl = Type.Payload.Bits{
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.base = .{ .tag = switch (int_info.signedness) {
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.signed => .int_signed,
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.unsigned => .int_unsigned,
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} },
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.data = @intCast(u16, @min(int_info.bits - byte_off * 8, limb_abi_size * 8)),
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};
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const limb_ty = Type.initPayload(&limb_pl.base);
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const limb_mcv = switch (byte_off) {
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0 => dst_mcv,
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else => dst_mcv.address().offset(byte_off).deref(),
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};
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if (limb_pl.base.tag == .int_unsigned and self.regExtraBits(limb_ty) > 0) {
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const mask = @as(u64, math.maxInt(u64)) >> @intCast(u6, 64 - limb_pl.data);
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try self.genBinOpMir(.xor, limb_ty, limb_mcv, .{ .immediate = mask });
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} else try self.genUnOpMir(.not, limb_ty, limb_mcv);
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}
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},
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.neg => try self.genUnOpMir(.neg, src_ty, dst_mcv),
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else => unreachable,
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}
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return dst_mcv;
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@ -4714,17 +4712,7 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue
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},
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.indirect, .load_frame => try self.asmMemory(
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mir_tag,
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Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (dst_mcv) {
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.indirect => |reg_off| .{
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.base = .{ .reg = reg_off.reg },
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.disp = reg_off.off,
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},
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.load_frame => |frame_addr| .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off,
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},
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else => unreachable,
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}),
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dst_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
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),
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}
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}
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@ -8179,12 +8167,9 @@ fn atomicOp(
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registerAlias(val_reg, cmov_abi_size),
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cc,
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),
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.load_frame => |frame_addr| try self.asmCmovccRegisterMemory(
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.memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory(
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registerAlias(tmp_reg, cmov_abi_size),
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Memory.sib(Memory.PtrSize.fromSize(cmov_abi_size), .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off,
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}),
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val_mcv.mem(Memory.PtrSize.fromSize(cmov_abi_size)),
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cc,
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),
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else => {
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@ -8207,72 +8192,62 @@ fn atomicOp(
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} else {
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try self.asmRegisterMemory(.mov, .rax, Memory.sib(.qword, .{
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.base = ptr_mem.sib.base,
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.scale_index = ptr_mem.sib.scale_index,
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.scale_index = ptr_mem.scaleIndex(),
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.disp = ptr_mem.sib.disp + 0,
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}));
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try self.asmRegisterMemory(.mov, .rdx, Memory.sib(.qword, .{
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.base = ptr_mem.sib.base,
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.scale_index = ptr_mem.sib.scale_index,
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.scale_index = ptr_mem.scaleIndex(),
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.disp = ptr_mem.sib.disp + 8,
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}));
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const loop = @intCast(u32, self.mir_instructions.len);
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switch (val_mcv) {
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.load_frame => |frame_addr| {
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const val_lo_mem = Memory.sib(.qword, .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off + 0,
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});
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const val_hi_mem = Memory.sib(.qword, .{
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.base = .{ .frame = frame_addr.index },
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.disp = frame_addr.off + 8,
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});
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if (rmw_op != std.builtin.AtomicRmwOp.Xchg) {
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try self.asmRegisterRegister(.mov, .rbx, .rax);
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try self.asmRegisterRegister(.mov, .rcx, .rdx);
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}
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if (rmw_op) |op| switch (op) {
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.Xchg => {
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try self.asmRegisterMemory(.mov, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.mov, .rcx, val_hi_mem);
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},
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.Add => {
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try self.asmRegisterMemory(.add, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.adc, .rcx, val_hi_mem);
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},
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.Sub => {
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try self.asmRegisterMemory(.sub, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.sbb, .rcx, val_hi_mem);
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},
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.And => {
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try self.asmRegisterMemory(.@"and", .rbx, val_lo_mem);
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try self.asmRegisterMemory(.@"and", .rcx, val_hi_mem);
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},
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.Nand => {
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try self.asmRegisterMemory(.@"and", .rbx, val_lo_mem);
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try self.asmRegisterMemory(.@"and", .rcx, val_hi_mem);
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try self.asmRegister(.not, .rbx);
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try self.asmRegister(.not, .rcx);
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},
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.Or => {
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try self.asmRegisterMemory(.@"or", .rbx, val_lo_mem);
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try self.asmRegisterMemory(.@"or", .rcx, val_hi_mem);
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},
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.Xor => {
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try self.asmRegisterMemory(.xor, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.xor, .rcx, val_hi_mem);
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},
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else => return self.fail(
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"TODO implement x86 atomic loop for large abi {s}",
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.{@tagName(op)},
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),
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};
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},
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else => return self.fail(
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"TODO implement x86 atomic loop for large abi {s}",
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.{@tagName(val_mcv)},
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),
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const val_mem_mcv: MCValue = switch (val_mcv) {
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.memory, .indirect, .load_frame => val_mcv,
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else => .{ .indirect = .{
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.reg = try self.copyToTmpRegister(Type.usize, val_mcv.address()),
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} },
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};
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const val_lo_mem = val_mem_mcv.mem(.qword);
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const val_hi_mem = val_mem_mcv.address().offset(8).deref().mem(.qword);
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if (rmw_op != std.builtin.AtomicRmwOp.Xchg) {
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try self.asmRegisterRegister(.mov, .rbx, .rax);
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try self.asmRegisterRegister(.mov, .rcx, .rdx);
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}
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if (rmw_op) |op| switch (op) {
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.Xchg => {
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try self.asmRegisterMemory(.mov, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.mov, .rcx, val_hi_mem);
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},
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.Add => {
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try self.asmRegisterMemory(.add, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.adc, .rcx, val_hi_mem);
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},
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.Sub => {
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try self.asmRegisterMemory(.sub, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.sbb, .rcx, val_hi_mem);
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},
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.And => {
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try self.asmRegisterMemory(.@"and", .rbx, val_lo_mem);
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try self.asmRegisterMemory(.@"and", .rcx, val_hi_mem);
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},
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.Nand => {
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try self.asmRegisterMemory(.@"and", .rbx, val_lo_mem);
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try self.asmRegisterMemory(.@"and", .rcx, val_hi_mem);
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try self.asmRegister(.not, .rbx);
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try self.asmRegister(.not, .rcx);
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},
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.Or => {
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try self.asmRegisterMemory(.@"or", .rbx, val_lo_mem);
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try self.asmRegisterMemory(.@"or", .rcx, val_hi_mem);
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},
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.Xor => {
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try self.asmRegisterMemory(.xor, .rbx, val_lo_mem);
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try self.asmRegisterMemory(.xor, .rcx, val_hi_mem);
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},
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else => return self.fail("TODO implement x86 atomic loop for {} {s}", .{
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val_ty.fmt(self.bin_file.options.module.?), @tagName(op),
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}),
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};
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_ = try self.addInst(.{ .tag = .cmpxchgb, .ops = .lock_m_sib, .data = .{
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.payload = try self.addExtra(Mir.MemorySib.encode(ptr_mem)),
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} });
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@ -9177,15 +9152,16 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
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}
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fn regBitSize(self: *Self, ty: Type) u64 {
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const abi_size = ty.abiSize(self.target.*);
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return switch (ty.zigTypeTag()) {
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else => switch (ty.abiSize(self.target.*)) {
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else => switch (abi_size) {
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1 => 8,
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2 => 16,
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3...4 => 32,
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5...8 => 64,
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else => unreachable,
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},
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.Float => switch (ty.abiSize(self.target.*)) {
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.Float => switch (abi_size) {
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1...16 => 128,
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17...32 => 256,
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else => unreachable,
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@ -9197,10 +9173,6 @@ fn regExtraBits(self: *Self, ty: Type) u64 {
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return self.regBitSize(ty) - ty.bitSize(self.target.*);
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}
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fn hasAvxSupport(target: Target) bool {
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return Target.x86.featureSetHasAny(target.cpu.features, .{ .avx, .avx2 });
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}
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fn getSymbolIndexForDecl(self: *Self, decl_index: Module.Decl.Index) !u32 {
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if (self.bin_file.cast(link.File.MachO)) |macho_file| {
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const atom = try macho_file.getOrCreateAtomForDecl(decl_index);
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@ -112,7 +112,6 @@ test "128-bit cmpxchg" {
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if (!supports_128_bit_atomics) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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@ -379,7 +379,6 @@ fn testBinaryNot(x: u16) !void {
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test "binary not 128-bit" {
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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