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std.atomic: add a function to get the cache line size for a particular cpu (#21956)
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@ -408,79 +408,87 @@ test spinLoopHint {
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}
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}
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pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
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return switch (cpu.arch) {
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// x86_64: Starting from Intel's Sandy Bridge, the spatial prefetcher pulls in pairs of 64-byte cache lines at a time.
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// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
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//
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// aarch64: Some big.LITTLE ARM archs have "big" cores with 128-byte cache lines:
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// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
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// - https://cpufun.substack.com/p/more-m1-fun-hardware-information
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//
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/arc/Kconfig#L212
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
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.x86_64,
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.aarch64,
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.aarch64_be,
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.arc,
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.powerpc64,
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.powerpc64le,
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=> 128,
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// https://github.com/llvm/llvm-project/blob/e379094328e49731a606304f7e3559d4f1fa96f9/clang/lib/Basic/Targets/Hexagon.h#L145-L151
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.hexagon,
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=> if (std.Target.hexagon.featureSetHas(cpu.features, .v73)) 64 else 32,
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
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.arm,
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.armeb,
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.thumb,
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.thumbeb,
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.riscv32,
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.riscv64,
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.sparc,
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.sparc64,
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=> 32,
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/m68k/include/asm/cache.h#L10
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.m68k,
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=> 16,
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// - https://www.ti.com/lit/pdf/slaa498
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.msp430,
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=> 8,
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
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// - https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf
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.s390x,
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.ve,
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=> 256,
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// Other x86 and WASM platforms have 64-byte cache lines.
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// The rest of the architectures are assumed to be similar.
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// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
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// - https://github.com/golang/go/blob/0a9321ad7f8c91e1b0c7184731257df923977eb9/src/internal/cpu/cpu_loong64.go#L11
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/xtensa/variants/csp/include/variant/core.h#L209
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/csky/Kconfig#L183
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// - https://www.xmos.com/download/The-XMOS-XS3-Architecture.pdf
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else => 64,
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};
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}
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/// The estimated size of the CPU's cache line when atomically updating memory.
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/// Add this much padding or align to this boundary to avoid atomically-updated
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/// memory from forcing cache invalidations on near, but non-atomic, memory.
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///
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/// https://en.wikipedia.org/wiki/False_sharing
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/// https://github.com/golang/go/search?q=CacheLinePadSize
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pub const cache_line = switch (builtin.cpu.arch) {
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// x86_64: Starting from Intel's Sandy Bridge, the spatial prefetcher pulls in pairs of 64-byte cache lines at a time.
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// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
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//
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// aarch64: Some big.LITTLE ARM archs have "big" cores with 128-byte cache lines:
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// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
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// - https://cpufun.substack.com/p/more-m1-fun-hardware-information
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//
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/arc/Kconfig#L212
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
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.x86_64,
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.aarch64,
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.aarch64_be,
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.arc,
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.powerpc64,
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.powerpc64le,
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=> 128,
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pub const cache_line = cacheLineForCpu(builtin.cpu);
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// https://github.com/llvm/llvm-project/blob/e379094328e49731a606304f7e3559d4f1fa96f9/clang/lib/Basic/Targets/Hexagon.h#L145-L151
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.hexagon,
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=> if (std.Target.hexagon.featureSetHas(builtin.target.cpu.features, .v73)) 64 else 32,
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
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.arm,
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.armeb,
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.thumb,
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.thumbeb,
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.riscv32,
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.riscv64,
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.sparc,
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.sparc64,
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=> 32,
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/m68k/include/asm/cache.h#L10
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.m68k,
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=> 16,
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// - https://www.ti.com/lit/pdf/slaa498
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.msp430,
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=> 8,
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
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// - https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf
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.s390x,
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.ve,
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=> 256,
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// Other x86 and WASM platforms have 64-byte cache lines.
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// The rest of the architectures are assumed to be similar.
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// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
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// - https://github.com/golang/go/blob/0a9321ad7f8c91e1b0c7184731257df923977eb9/src/internal/cpu/cpu_loong64.go#L11
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/xtensa/variants/csp/include/variant/core.h#L209
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// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/csky/Kconfig#L183
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// - https://www.xmos.com/download/The-XMOS-XS3-Architecture.pdf
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else => 64,
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};
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test "current CPU has a cache line size" {
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_ = cache_line;
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}
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const std = @import("std.zig");
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const builtin = @import("builtin");
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