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x86_64: implement @splat
This commit is contained in:
Jacob Young
parent
1336619979
commit
c23e80e671
@ -8561,7 +8561,8 @@ fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.FixedTag {
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},
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32 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
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2...4 => return if (self.hasFeature(.avx))
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2 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
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3...4 => return if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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5...8 => if (self.hasFeature(.avx))
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@ -8577,6 +8578,14 @@ fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.FixedTag {
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return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
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else => {},
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},
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128 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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2 => if (self.hasFeature(.avx))
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return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
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else => {},
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},
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else => {},
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},
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else => {},
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@ -9939,9 +9948,200 @@ fn airErrorName(self: *Self, inst: Air.Inst.Index) !void {
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fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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_ = ty_op;
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return self.fail("TODO implement airSplat for x86_64", .{});
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//return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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const vector_ty = self.air.typeOfIndex(inst);
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const dst_rc = regClassForType(vector_ty);
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const scalar_ty = vector_ty.scalarType();
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const src_mcv = try self.resolveInst(ty_op.operand);
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const result: MCValue = result: {
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switch (scalar_ty.zigTypeTag()) {
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else => {},
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.Float => switch (scalar_ty.floatBits(self.target.*)) {
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32 => switch (vector_ty.vectorLen()) {
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1 => {
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if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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try self.genSetReg(dst_reg, scalar_ty, src_mcv);
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break :result .{ .register = dst_reg };
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},
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2...4 => {
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if (self.hasFeature(.avx)) {
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_ss, .broadcast },
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dst_reg.to128(),
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src_mcv.mem(.dword),
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) else {
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const src_reg = if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(scalar_ty, src_mcv);
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try self.asmRegisterRegisterRegisterImmediate(
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.{ .v_ps, .shuf },
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dst_reg.to128(),
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src_reg.to128(),
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src_reg.to128(),
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Immediate.u(0),
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);
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}
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break :result .{ .register = dst_reg };
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} else {
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const dst_mcv = if (src_mcv.isRegister() and
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self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
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src_mcv
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else
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try self.copyToRegisterWithInstTracking(inst, scalar_ty, src_mcv);
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const dst_reg = dst_mcv.getReg().?;
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try self.asmRegisterRegisterImmediate(
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.{ ._ps, .shuf },
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dst_reg.to128(),
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dst_reg.to128(),
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Immediate.u(0),
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);
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break :result dst_mcv;
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}
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},
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5...8 => if (self.hasFeature(.avx)) {
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_ss, .broadcast },
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dst_reg.to256(),
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src_mcv.mem(.dword),
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) else {
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const src_reg = if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(scalar_ty, src_mcv);
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if (self.hasFeature(.avx2)) try self.asmRegisterRegister(
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.{ .v_ss, .broadcast },
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dst_reg.to256(),
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src_reg.to128(),
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) else {
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try self.asmRegisterRegisterRegisterImmediate(
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.{ .v_ps, .shuf },
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dst_reg.to128(),
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src_reg.to128(),
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src_reg.to128(),
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Immediate.u(0),
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);
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try self.asmRegisterRegisterRegisterImmediate(
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.{ .v_f128, .insert },
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dst_reg.to256(),
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dst_reg.to256(),
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dst_reg.to128(),
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Immediate.u(1),
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);
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}
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}
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break :result .{ .register = dst_reg };
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},
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else => {},
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},
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64 => switch (vector_ty.vectorLen()) {
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1 => {
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if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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try self.genSetReg(dst_reg, scalar_ty, src_mcv);
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break :result .{ .register = dst_reg };
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},
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2 => {
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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if (self.hasFeature(.sse3)) {
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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if (self.hasFeature(.avx)) .{ .v_, .movddup } else .{ ._, .movddup },
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dst_reg.to128(),
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src_mcv.mem(.qword),
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) else try self.asmRegisterRegister(
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if (self.hasFeature(.avx)) .{ .v_, .movddup } else .{ ._, .movddup },
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dst_reg.to128(),
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(scalar_ty, src_mcv)).to128(),
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);
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break :result .{ .register = dst_reg };
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} else try self.asmRegisterRegister(
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.{ ._ps, .movlh },
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dst_reg.to128(),
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(if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(scalar_ty, src_mcv)).to128(),
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);
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},
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3...4 => if (self.hasFeature(.avx)) {
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_sd, .broadcast },
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dst_reg.to256(),
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src_mcv.mem(.qword),
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) else {
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const src_reg = if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(scalar_ty, src_mcv);
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if (self.hasFeature(.avx2)) try self.asmRegisterRegister(
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.{ .v_sd, .broadcast },
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dst_reg.to256(),
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src_reg.to128(),
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) else {
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try self.asmRegisterRegister(
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.{ .v_, .movddup },
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dst_reg.to128(),
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src_reg.to128(),
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);
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try self.asmRegisterRegisterRegisterImmediate(
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.{ .v_f128, .insert },
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dst_reg.to256(),
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dst_reg.to256(),
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dst_reg.to128(),
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Immediate.u(1),
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);
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}
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}
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break :result .{ .register = dst_reg };
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},
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else => {},
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},
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128 => switch (vector_ty.vectorLen()) {
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1 => {
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if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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try self.genSetReg(dst_reg, scalar_ty, src_mcv);
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break :result .{ .register = dst_reg };
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},
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2 => if (self.hasFeature(.avx)) {
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const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
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if (src_mcv.isMemory()) try self.asmRegisterMemory(
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.{ .v_f128, .broadcast },
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dst_reg.to256(),
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src_mcv.mem(.xword),
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) else {
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const src_reg = if (src_mcv.isRegister())
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src_mcv.getReg().?
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else
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try self.copyToTmpRegister(scalar_ty, src_mcv);
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try self.asmRegisterRegisterRegisterImmediate(
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.{ .v_f128, .insert },
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dst_reg.to256(),
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src_reg.to256(),
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src_reg.to128(),
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Immediate.u(1),
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);
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}
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break :result .{ .register = dst_reg };
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},
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else => {},
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},
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16, 80 => {},
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else => unreachable,
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},
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}
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return self.fail("TODO implement airSplat for {}", .{
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vector_ty.fmt(self.bin_file.options.module.?),
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});
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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fn airSelect(self: *Self, inst: Air.Inst.Index) !void {
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@ -270,10 +270,12 @@ pub const Mnemonic = enum {
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divps, divss,
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maxps, maxss,
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minps, minss,
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movaps, movhlps, movss, movups,
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movaps, movhlps, movlhps,
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movss, movups,
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mulps, mulss,
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orps,
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pextrw, pinsrw,
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shufps,
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sqrtps, sqrtss,
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subps, subss,
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ucomiss,
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@ -296,6 +298,7 @@ pub const Mnemonic = enum {
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psrld, psrlq, psrlw,
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punpckhbw, punpckhdq, punpckhqdq, punpckhwd,
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punpcklbw, punpckldq, punpcklqdq, punpcklwd,
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shufpd,
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sqrtpd, sqrtsd,
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subpd, subsd,
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ucomisd,
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@ -303,17 +306,22 @@ pub const Mnemonic = enum {
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// SSE3
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movddup, movshdup, movsldup,
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// SSE4.1
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extractps,
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insertps,
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pextrb, pextrd, pextrq,
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pinsrb, pinsrd, pinsrq,
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roundpd, roundps, roundsd, roundss,
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// AVX
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vaddpd, vaddps, vaddsd, vaddss,
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vbroadcastf128, vbroadcastsd, vbroadcastss,
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vcvtsd2ss, vcvtsi2sd, vcvtsi2ss, vcvtss2sd,
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vdivpd, vdivps, vdivsd, vdivss,
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vextractf128, vextractps,
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vinsertf128, vinsertps,
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vmaxpd, vmaxps, vmaxsd, vmaxss,
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vminpd, vminps, vminsd, vminss,
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vmovapd, vmovaps,
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vmovddup, vmovhlps,
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vmovddup, vmovhlps, vmovlhps,
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vmovsd,
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vmovshdup, vmovsldup,
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vmovss,
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@ -326,6 +334,7 @@ pub const Mnemonic = enum {
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vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
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vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
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vroundpd, vroundps, vroundsd, vroundss,
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vshufpd, vshufps,
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vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,
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vsubpd, vsubps, vsubsd, vsubss,
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// F16C
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@ -300,6 +300,8 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void {
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else
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.none,
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}, mnemonic: {
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@setEvalBranchQuota(2_000);
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comptime var max_len = 0;
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inline for (@typeInfo(Mnemonic).Enum.fields) |field| max_len = @max(field.name.len, max_len);
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var buf: [max_len]u8 = undefined;
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@ -256,6 +256,8 @@ pub const Inst = struct {
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v_sd,
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/// VEX-Encoded ___ Packed Double-Precision Values
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v_pd,
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/// VEX-Encoded ___ 128-Bits Of Floating-Point Data
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v_f128,
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/// Mask ___ Byte
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k_b,
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@ -454,6 +456,8 @@ pub const Inst = struct {
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mova,
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/// Move packed single-precision floating-point values high to low
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movhl,
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/// Move packed single-precision floating-point values low to high
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movlh,
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/// Move unaligned packed single-precision floating-point values
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/// Move unaligned packed double-precision floating-point values
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movu,
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@ -488,6 +492,9 @@ pub const Inst = struct {
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cvtsi2sd,
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/// Convert scalar single-precision floating-point value to scalar double-precision floating-point value
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cvtss2sd,
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/// Packed interleave shuffle of quadruplets of single-precision floating-point values
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/// Packed interleave shuffle of pairs of double-precision floating-point values
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shuf,
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/// Shuffle packed high words
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shufh,
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/// Shuffle packed low words
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@ -520,12 +527,20 @@ pub const Inst = struct {
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/// Replicate single floating-point values
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movsldup,
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/// Extract packed floating-point values
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extract,
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/// Insert scalar single-precision floating-point value
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/// Insert packed floating-point values
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insert,
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/// Round packed single-precision floating-point values
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/// Round scalar single-precision floating-point value
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/// Round packed double-precision floating-point values
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/// Round scalar double-precision floating-point value
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round,
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/// Load with broadcast floating-point data
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broadcast,
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/// Convert 16-bit floating-point values to single-precision floating-point values
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cvtph2ps,
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/// Convert single-precision floating-point values to 16-bit floating-point values
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@ -867,6 +867,8 @@ pub const table = [_]Entry{
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.{ .movhlps, .rm, &.{ .xmm, .xmm }, &.{ 0x0f, 0x12 }, 0, .none, .sse },
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.{ .movlhps, .rm, &.{ .xmm, .xmm }, &.{ 0x0f, 0x16 }, 0, .none, .sse },
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.{ .movss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .none, .sse },
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.{ .movss, .mr, &.{ .xmm_m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .none, .sse },
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@ -879,14 +881,16 @@ pub const table = [_]Entry{
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.{ .orps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x56 }, 0, .none, .sse },
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.{ .subps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x5c }, 0, .none, .sse },
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.{ .subss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .none, .sse },
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.{ .shufps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x0f, 0xc6 }, 0, .none, .sse },
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.{ .sqrtps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x51 }, 0, .none, .sse },
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.{ .sqrtss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x51 }, 0, .none, .sse },
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.{ .subps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x5c }, 0, .none, .sse },
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.{ .subss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .none, .sse },
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.{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .none, .sse },
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.{ .xorps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x57 }, 0, .none, .sse },
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@ -967,6 +971,8 @@ pub const table = [_]Entry{
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.{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
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.{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },
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.{ .shufpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc6 }, 0, .none, .sse2 },
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.{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },
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.{ .sqrtsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x51 }, 0, .none, .sse2 },
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@ -990,6 +996,10 @@ pub const table = [_]Entry{
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.{ .movsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .none, .sse3 },
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// SSE4.1
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.{ .extractps, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x17 }, 0, .none, .sse4_1 },
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.{ .insertps, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x21 }, 0, .none, .sse4_1 },
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.{ .pextrb, .mri, &.{ .r32_m8, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x14 }, 0, .none, .sse4_1 },
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.{ .pextrd, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .none, .sse4_1 },
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.{ .pextrq, .mri, &.{ .rm64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .long, .sse4_1 },
|
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@ -1019,6 +1029,11 @@ pub const table = [_]Entry{
|
||||
|
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.{ .vaddss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .vex_lig_wig, .avx },
|
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||||
.{ .vbroadcastss, .rm, &.{ .xmm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx },
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.{ .vbroadcastss, .rm, &.{ .ymm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx },
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||||
.{ .vbroadcastsd, .rm, &.{ .ymm, .m64 }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx },
|
||||
.{ .vbroadcastf128, .rm, &.{ .ymm, .m128 }, &.{ 0x66, 0x0f, 0x38, 0x1a }, 0, .vex_256_w0, .avx },
|
||||
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||||
.{ .vcvtsd2ss, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .vex_lig_wig, .avx },
|
||||
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||||
.{ .vcvtsi2sd, .rvm, &.{ .xmm, .xmm, .rm32 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w0, .avx },
|
||||
@ -1039,6 +1054,14 @@ pub const table = [_]Entry{
|
||||
|
||||
.{ .vdivss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5e }, 0, .vex_lig_wig, .avx },
|
||||
|
||||
.{ .vextractf128, .mri, &.{ .xmm_m128, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x19 }, 0, .vex_256_w0, .avx },
|
||||
|
||||
.{ .vextractps, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x17 }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vinsertf128, .rvmi, &.{ .ymm, .ymm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x18 }, 0, .vex_256_w0, .avx },
|
||||
|
||||
.{ .vinsertps, .rvmi, &.{ .xmm, .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x21 }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vmaxpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x5f }, 0, .vex_128_wig, .avx },
|
||||
.{ .vmaxpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x5f }, 0, .vex_256_wig, .avx },
|
||||
|
||||
@ -1074,6 +1097,8 @@ pub const table = [_]Entry{
|
||||
|
||||
.{ .vmovhlps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vmovlhps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x16 }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
|
||||
.{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
|
||||
.{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
|
||||
@ -1150,6 +1175,12 @@ pub const table = [_]Entry{
|
||||
|
||||
.{ .vroundss, .rvmi, &.{ .xmm, .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .vex_lig_wig, .avx },
|
||||
|
||||
.{ .vshufpd, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc6 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vshufpd, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0xc6 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vshufps, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x0f, 0xc6 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vshufps, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x0f, 0xc6 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vsqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vsqrtpd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x51 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
@ -1201,6 +1232,10 @@ pub const table = [_]Entry{
|
||||
.{ .vfmadd231ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_lig_w0, .fma },
|
||||
|
||||
// AVX2
|
||||
.{ .vbroadcastss, .rm, &.{ .xmm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx2 },
|
||||
.{ .vbroadcastss, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx2 },
|
||||
.{ .vbroadcastsd, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx2 },
|
||||
|
||||
.{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },
|
||||
.{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },
|
||||
.{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user