diff --git a/std/os/linux/arm-eabi.zig b/std/os/linux/arm-eabi.zig
index a8cb52d711..1167c10f0b 100644
--- a/std/os/linux/arm-eabi.zig
+++ b/std/os/linux/arm-eabi.zig
@@ -80,7 +80,8 @@ pub fn syscall6(
 pub extern fn clone(func: extern fn (arg: usize) u8, stack: usize, flags: u32, arg: usize, ptid: *i32, tls: usize, ctid: *i32) usize;
 
 // LLVM calls this when the read-tp-hard feature is set to false. Currently, there is no way to pass
-// that to llvm via zig. See https://github.com/ziglang/zig/issues/2883
+// that to llvm via zig, see https://github.com/ziglang/zig/issues/2883.
+// LLVM expects libc to provide this function as __aeabi_read_tp, so it is exported if needed from special/c.zig.
 pub nakedcc fn getThreadPointer() usize {
     return asm volatile("mrc p15, 0, %[ret], c13, c0, 3"
         : [ret] "=r" (-> usize)
diff --git a/std/os/linux/tls.zig b/std/os/linux/tls.zig
index a14b26a5cf..1b2687b82c 100644
--- a/std/os/linux/tls.zig
+++ b/std/os/linux/tls.zig
@@ -150,9 +150,9 @@ pub fn initTLS() void {
     if (builtin.arch == builtin.Arch.arm and builtin.os == .linux) {
         if (at_hwcap & std.os.linux.HWCAP_TLS == 0) {
             // If the CPU does not support TLS via a coprocessor register,
-            // it could be accessed via a kernel helper function
-            // see musl/src/thread/arm/ for details
-            @panic("cpu does not support TLS via coprocessor register");
+            // a kernel helper function can be used instead on certain linux kernels.
+            // See linux/arch/arm/include/asm/tls.h and musl/src/thread/arm/__set_thread_area.c.
+            @panic("TODO: Implement ARM fallback TLS functionality");
         }
     }