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riscv: implement non-pow2 indirect loads

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This commit is contained in:
David Rubin 2024-07-31 14:00:46 -07:00 committed by Andrew Kelley
parent a69d403cb2
commit c08effc20a
2 changed files with 4 additions and 5 deletions
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8
src/arch/riscv64/CodeGen.zig
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@ -6855,10 +6855,10 @@ fn genSetReg(func: *Func, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
else => return std.debug.panic("TODO: genSetReg for float size {d}", .{abi_size}),
},
.int => switch (abi_size) {
1 => .lb,
2 => .lh,
4 => .lw,
8 => .ld,
1...1 => .lb,
2...2 => .lh,
3...4 => .lw,
5...8 => .ld,
else => return std.debug.panic("TODO: genSetReg for int size {d}", .{abi_size}),
},
.vector => {

1
test/behavior/defer.zig
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@ -94,7 +94,6 @@ test "mixing normal and error defers" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
try expect(runSomeErrorDefers(true) catch unreachable);
try expect(result[0] == 'c');