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https://github.com/ziglang/zig.git
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stage2,x64: impl lowering of shift ops in Emit
This commit is contained in:
Jakub Konka
parent
7a9b9df80e
commit
becbf446d3
@ -2037,17 +2037,42 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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break :result MCValue{ .stack_offset = stack_offset };
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},
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.register => |reg| {
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// 1. Shift by struct_field_offset.
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// 2. Mask with reg.size() - struct_field_size
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// 3. Return in register
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// TODO check if register can be re-used
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self.register_manager.freezeRegs(&.{reg});
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defer self.register_manager.unfreezeRegs(&.{reg});
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const dst_mcv = blk: {
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if (self.reuseOperand(inst, operand, 0, mcv)) {
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break :blk mcv;
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} else {
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const dst_mcv = try self.copyToNewRegister(inst, Type.usize, .{ .register = reg.to64() });
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break :blk dst_mcv;
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}
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};
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// TODO shift here
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// Shift by struct_field_offset.
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const shift_amount = @intCast(u8, struct_field_offset * 8);
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if (shift_amount > 0) {
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if (shift_amount == 1) {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = dst_mcv.register,
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}).encode(),
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.data = undefined,
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});
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} else {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = dst_mcv.register,
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift_amount },
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});
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}
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}
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// Mask with reg.size() - struct_field_size
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const mask_shift = @intCast(u6, (64 - struct_field_ty.bitSize(self.target.*)));
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const mask = (~@as(u64, 0)) >> mask_shift;
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try self.genBinMathOpMir(.@"and", Type.usize, dst_mcv, .{ .immediate = mask });
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@ -133,6 +133,11 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
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.lea => try emit.mirLea(inst),
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.lea_pie => try emit.mirLeaPie(inst),
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.shl => try emit.mirShift(.shl, inst),
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.sal => try emit.mirShift(.sal, inst),
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.shr => try emit.mirShift(.shr, inst),
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.sar => try emit.mirShift(.sar, inst),
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.imul_complex => try emit.mirIMulComplex(inst),
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.push => try emit.mirPushPop(.push, inst),
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@ -653,6 +658,31 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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return lowerToFdEnc(.mov, ops.reg1, imm, emit.code);
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}
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fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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// sal reg1, 1
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// M1
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return lowerToM1Enc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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},
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0b01 => {
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// sal reg1, .cl
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// MC
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return lowerToMcEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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},
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0b10 => {
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// sal reg1, imm8
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// MI
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const imm = @truncate(u8, emit.mir.instructions.items(.data)[inst].imm);
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return lowerToMiImm8Enc(tag, RegisterOrMemory.reg(ops.reg1), imm, emit.code);
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},
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0b11 => {
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return emit.fail("TODO unused variant: SHIFT reg1, 0b11", .{});
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},
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}
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}
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fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .imul_complex);
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@ -743,13 +773,13 @@ fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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emit.code,
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);
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const end_offset = emit.code.items.len;
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const sym_index = emit.mir.instructions.items(.data)[inst].linker_sym_index;
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if (emit.bin_file.cast(link.File.MachO)) |macho_file| {
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const reloc_type = switch (ops.flags) {
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0b00 => @enumToInt(std.macho.reloc_type_x86_64.X86_64_RELOC_GOT),
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0b01 => @enumToInt(std.macho.reloc_type_x86_64.X86_64_RELOC_SIGNED),
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else => return emit.fail("TODO unused LEA PIE variants 0b10 and 0b11", .{}),
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};
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const sym_index = emit.mir.instructions.items(.data)[inst].linker_sym_index;
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if (emit.bin_file.cast(link.File.MachO)) |macho_file| {
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const decl = macho_file.active_decl.?;
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try decl.link.macho.relocs.append(emit.bin_file.allocator, .{
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.offset = @intCast(u32, end_offset - 4),
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@ -1064,6 +1094,10 @@ const Tag = enum {
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setng,
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setnle,
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setg,
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shl,
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sal,
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shr,
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sar,
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fn isSetCC(tag: Tag) bool {
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return switch (tag) {
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@ -1119,9 +1153,18 @@ const Encoding = enum {
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/// OP imm32
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i,
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/// OP r/m64, 1
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m1,
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/// OP r/m64, .cl
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mc,
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/// OP r/m64, imm32
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mi,
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/// OP r/m64, imm8
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mi8,
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/// OP r/m64, r64
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mr,
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@ -1230,12 +1273,25 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
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.ret_far => OpCode.oneByte(0xca),
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else => null,
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},
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.m1 => return switch (tag) {
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.shl, .sal, .shr, .sar => OpCode.oneByte(if (is_one_byte) 0xd0 else 0xd1),
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else => null,
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},
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.mc => return switch (tag) {
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.shl, .sal, .shr, .sar => OpCode.oneByte(if (is_one_byte) 0xd2 else 0xd3),
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else => null,
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},
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.mi => return switch (tag) {
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.adc, .add, .sub, .xor, .@"and", .@"or", .sbb, .cmp => OpCode.oneByte(if (is_one_byte) 0x80 else 0x81),
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.mov => OpCode.oneByte(if (is_one_byte) 0xc6 else 0xc7),
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.@"test" => OpCode.oneByte(if (is_one_byte) 0xf6 else 0xf7),
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else => null,
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},
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.mi8 => return switch (tag) {
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.adc, .add, .sub, .xor, .@"and", .@"or", .sbb, .cmp => OpCode.oneByte(0x83),
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.shl, .sal, .shr, .sar => OpCode.oneByte(if (is_one_byte) 0xc0 else 0xc1),
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else => null,
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},
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.mr => return switch (tag) {
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.adc => OpCode.oneByte(if (is_one_byte) 0x10 else 0x11),
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.add => OpCode.oneByte(if (is_one_byte) 0x00 else 0x01),
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@ -1331,6 +1387,11 @@ inline fn getModRmExt(tag: Tag) ?u3 {
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.setnle,
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.setg,
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=> 0x0,
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.shl,
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.sal,
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=> 0x4,
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.shr => 0x5,
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.sar => 0x7,
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else => null,
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};
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}
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@ -1528,8 +1589,8 @@ fn lowerToDEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
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encoder.imm32(@bitCast(i32, imm));
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}
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fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8)) InnerError!void {
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const opc = getOpCode(tag, .m, false).?;
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fn lowerToMxEnc(tag: Tag, reg_or_mem: RegisterOrMemory, enc: Encoding, code: *std.ArrayList(u8)) InnerError!void {
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const opc = getOpCode(tag, enc, reg_or_mem.size() == 8).?;
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const modrm_ext = getModRmExt(tag).?;
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switch (reg_or_mem) {
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.register => |reg| {
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@ -1537,11 +1598,9 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
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if (reg.size() == 16) {
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encoder.prefix16BitMode();
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}
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const wide = if (tag == .jmp_near) false else setRexWRegister(reg);
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encoder.rex(.{
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.w = switch (reg) {
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.ah, .bh, .ch, .dh => true,
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else => false,
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},
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.w = wide,
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.b = reg.isExtended(),
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});
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opc.encode(encoder);
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@ -1553,8 +1612,9 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
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encoder.prefix16BitMode();
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}
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if (mem_op.base) |base| {
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const wide = if (tag == .jmp_near) false else mem_op.ptr_size == .qword_ptr;
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encoder.rex(.{
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.w = false,
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.w = wide,
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.b = base.isExtended(),
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});
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}
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@ -1564,6 +1624,18 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
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}
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}
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fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8)) InnerError!void {
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return lowerToMxEnc(tag, reg_or_mem, .m, code);
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}
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fn lowerToM1Enc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8)) InnerError!void {
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return lowerToMxEnc(tag, reg_or_mem, .m1, code);
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}
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fn lowerToMcEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8)) InnerError!void {
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return lowerToMxEnc(tag, reg_or_mem, .mc, code);
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}
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fn lowerToTdEnc(tag: Tag, moffs: u64, reg: Register, code: *std.ArrayList(u8)) InnerError!void {
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return lowerToTdFdEnc(tag, reg, moffs, code, true);
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}
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@ -1614,9 +1686,15 @@ fn lowerToOiEnc(tag: Tag, reg: Register, imm: u64, code: *std.ArrayList(u8)) Inn
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}
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}
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fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
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fn lowerToMiXEnc(
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tag: Tag,
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reg_or_mem: RegisterOrMemory,
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imm: u32,
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enc: Encoding,
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code: *std.ArrayList(u8),
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) InnerError!void {
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const modrm_ext = getModRmExt(tag).?;
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const opc = getOpCode(tag, .mi, reg_or_mem.size() == 8).?;
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const opc = getOpCode(tag, enc, reg_or_mem.size() == 8).?;
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switch (reg_or_mem) {
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.register => |dst_reg| {
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const encoder = try Encoder.init(code, 7);
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@ -1632,7 +1710,7 @@ fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: u32, code: *std.Arr
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});
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opc.encode(encoder);
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encoder.modRm_direct(modrm_ext, dst_reg.lowId());
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encodeImm(encoder, imm, dst_reg.size());
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encodeImm(encoder, imm, if (enc == .mi8) 8 else dst_reg.size());
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},
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.memory => |dst_mem| {
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const encoder = try Encoder.init(code, 12);
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@ -1651,11 +1729,19 @@ fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: u32, code: *std.Arr
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}
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opc.encode(encoder);
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dst_mem.encode(encoder, modrm_ext);
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encodeImm(encoder, imm, dst_mem.ptr_size.size());
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encodeImm(encoder, imm, if (enc == .mi8) 8 else dst_mem.ptr_size.size());
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},
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}
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}
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fn lowerToMiImm8Enc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: u8, code: *std.ArrayList(u8)) InnerError!void {
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return lowerToMiXEnc(tag, reg_or_mem, imm, .mi8, code);
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}
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fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
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return lowerToMiXEnc(tag, reg_or_mem, imm, .mi, code);
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}
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fn lowerToRmEnc(
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tag: Tag,
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reg: Register,
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@ -1902,6 +1988,9 @@ test "lower MI encoding" {
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emit.lowered(),
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"mov qword ptr [rcx*2 + 0x10000000], 0x10",
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);
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try lowerToMiImm8Enc(.add, RegisterOrMemory.reg(.rax), 0x10, emit.code());
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try expectEqualHexStrings("\x48\x83\xC0\x10", emit.lowered(), "add rax, 0x10");
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}
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test "lower RM encoding" {
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@ -2100,6 +2189,41 @@ test "lower M encoding" {
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try expectEqualHexStrings("\x41\x0F\x97\xC3", emit.lowered(), "seta r11b");
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}
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test "lower M1 and MC encodings" {
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var emit = TestEmit.init();
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defer emit.deinit();
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try lowerToM1Enc(.sal, RegisterOrMemory.reg(.r12), emit.code());
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try expectEqualHexStrings("\x49\xD1\xE4", emit.lowered(), "sal r12, 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.reg(.r12d), emit.code());
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try expectEqualHexStrings("\x41\xD1\xE4", emit.lowered(), "sal r12d, 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.reg(.r12w), emit.code());
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try expectEqualHexStrings("\x66\x41\xD1\xE4", emit.lowered(), "sal r12w, 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.reg(.r12b), emit.code());
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try expectEqualHexStrings("\x41\xD0\xE4", emit.lowered(), "sal r12b, 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.reg(.rax), emit.code());
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try expectEqualHexStrings("\x48\xD1\xE0", emit.lowered(), "sal rax, 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.reg(.eax), emit.code());
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try expectEqualHexStrings("\xD1\xE0", emit.lowered(), "sal eax, 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = @bitCast(u32, @as(i32, -0x10)),
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.base = .rbp,
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}), emit.code());
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try expectEqualHexStrings("\x48\xD1\x65\xF0", emit.lowered(), "sal qword ptr [rbp - 0x10], 1");
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try lowerToM1Enc(.sal, RegisterOrMemory.mem(.dword_ptr, .{
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.disp = @bitCast(u32, @as(i32, -0x10)),
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.base = .rbp,
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}), emit.code());
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try expectEqualHexStrings("\xD1\x65\xF0", emit.lowered(), "sal dword ptr [rbp - 0x10], 1");
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try lowerToMcEnc(.shr, RegisterOrMemory.reg(.r12), emit.code());
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try expectEqualHexStrings("\x49\xD3\xEC", emit.lowered(), "shr r12, cl");
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try lowerToMcEnc(.shr, RegisterOrMemory.reg(.rax), emit.code());
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try expectEqualHexStrings("\x48\xD3\xE8", emit.lowered(), "shr rax, cl");
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try lowerToMcEnc(.sar, RegisterOrMemory.reg(.rsi), emit.code());
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try expectEqualHexStrings("\x48\xD3\xFE", emit.lowered(), "sar rsi, cl");
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}
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test "lower O encoding" {
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var emit = TestEmit.init();
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defer emit.deinit();
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@ -142,30 +142,6 @@ pub const Inst = struct {
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rcr_scale_dst,
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rcr_scale_imm,
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rcr_mem_index_imm,
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shl,
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shl_mem_imm,
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shl_scale_src,
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shl_scale_dst,
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shl_scale_imm,
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shl_mem_index_imm,
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sal,
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sal_mem_imm,
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sal_scale_src,
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sal_scale_dst,
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sal_scale_imm,
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sal_mem_index_imm,
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shr,
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shr_mem_imm,
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shr_scale_src,
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shr_scale_dst,
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shr_scale_imm,
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shr_mem_index_imm,
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sar,
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sar_mem_imm,
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sar_scale_src,
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sar_scale_dst,
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sar_scale_imm,
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sar_mem_index_imm,
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sbb,
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sbb_mem_imm,
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sbb_scale_src,
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@ -212,6 +188,37 @@ pub const Inst = struct {
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/// * `Data` contains `linker_sym_index`
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lea_pie,
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/// ops flags: form:
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/// 0b00 reg1, 1
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/// 0b01 reg1, .cl
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/// 0b10 reg1, imm8
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/// Notes:
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/// * If flags == 0b10, uses `imm`.
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shl,
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shl_mem_imm,
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shl_scale_src,
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shl_scale_dst,
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shl_scale_imm,
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shl_mem_index_imm,
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sal,
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sal_mem_imm,
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sal_scale_src,
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sal_scale_dst,
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sal_scale_imm,
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sal_mem_index_imm,
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shr,
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shr_mem_imm,
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shr_scale_src,
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shr_scale_dst,
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shr_scale_imm,
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shr_mem_index_imm,
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sar,
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sar_mem_imm,
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sar_scale_src,
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sar_scale_dst,
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sar_scale_imm,
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sar_mem_index_imm,
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/// ops flags: form:
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/// 0bX0 reg1
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/// 0bX1 [reg1 + imm32]
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@ -372,7 +372,6 @@ pub fn generateSymbol(
|
||||
return Result{ .appended = {} };
|
||||
},
|
||||
.Struct => {
|
||||
// TODO debug info
|
||||
const struct_obj = typed_value.ty.castTag(.@"struct").?.data;
|
||||
if (struct_obj.layout == .Packed) {
|
||||
return Result{
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user