diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index e727596ed5..e1cc9470cb 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -9977,12 +9977,25 @@ fn genBinOp(
             defer self.register_manager.unlockReg(gp_lock);
 
             try self.asmRegisterRegister(switch (mir_tag[0]) {
-                ._pd, ._sd => .{ ._pd, .movmsk },
-                ._ps, ._ss => .{ ._ps, .movmsk },
-                .p_b, .p_d, .p_q, .p_w => .{ .p_b, .movmsk },
-                .v_pd, .v_sd => .{ .v_pd, .movmsk },
-                .v_ps, .v_ss => .{ .v_ps, .movmsk },
-                .vp_b, .vp_d, .vp_q, .vp_w => .{ .vp_b, .movmsk },
+                ._pd, ._sd, .p_q => .{ ._pd, .movmsk },
+                ._ps, ._ss, .p_d => .{ ._ps, .movmsk },
+                .p_b => .{ .p_b, .movmsk },
+                .p_w => movmsk: {
+                    try self.asmRegisterRegister(.{ .p_b, .ackssw }, dst_reg, dst_reg);
+                    break :movmsk .{ .p_b, .movmsk };
+                },
+                .v_pd, .v_sd, .vp_q => .{ .v_pd, .movmsk },
+                .v_ps, .v_ss, .vp_d => .{ .v_ps, .movmsk },
+                .vp_b => .{ .vp_b, .movmsk },
+                .vp_w => movmsk: {
+                    try self.asmRegisterRegisterRegister(
+                        .{ .vp_b, .ackssw },
+                        dst_reg,
+                        dst_reg,
+                        dst_reg,
+                    );
+                    break :movmsk .{ .vp_b, .movmsk };
+                },
                 else => unreachable,
             }, gp_reg.to32(), dst_reg);
             return .{ .register = gp_reg };
diff --git a/test/behavior/math.zig b/test/behavior/math.zig
index ab54c9e4a9..3d3c282854 100644
--- a/test/behavior/math.zig
+++ b/test/behavior/math.zig
@@ -78,12 +78,11 @@ fn testClz() !void {
 }
 
 test "@clz big ints" {
-    if (builtin.zig_backend == .stage2_x86_64 and
-        !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .lzcnt)) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
+    if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
 
     try testClzBigInts();
     try comptime testClzBigInts();
@@ -1610,8 +1609,9 @@ test "vector comparison" {
     if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
-    if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
+    if (builtin.zig_backend == .stage2_x86_64 and
+        !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .avx2)) return error.SkipZigTest;
 
     const S = struct {
         fn doTheTest() !void {
diff --git a/test/behavior/vector.zig b/test/behavior/vector.zig
index 667bf3d898..4ae7e76c74 100644
--- a/test/behavior/vector.zig
+++ b/test/behavior/vector.zig
@@ -49,7 +49,6 @@ test "vector wrap operators" {
 
 test "vector bin compares with mem.eql" {
     if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
-    if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO