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initial implementation of print_mir
This commit is contained in:
Jacob G-W
parent
c9352ef9d6
commit
bd19f5e611
@ -81,6 +81,7 @@ clang_preprocessor_mode: ClangPreprocessorMode,
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/// Whether to print clang argvs to stdout.
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verbose_cc: bool,
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verbose_air: bool,
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verbose_mir: bool,
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verbose_llvm_ir: bool,
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verbose_cimport: bool,
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verbose_llvm_cpu_features: bool,
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@ -743,6 +744,7 @@ pub const InitOptions = struct {
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verbose_cc: bool = false,
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verbose_link: bool = false,
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verbose_air: bool = false,
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verbose_mir: bool = false,
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verbose_llvm_ir: bool = false,
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verbose_cimport: bool = false,
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verbose_llvm_cpu_features: bool = false,
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@ -1526,6 +1528,7 @@ pub fn create(gpa: *Allocator, options: InitOptions) !*Compilation {
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.clang_preprocessor_mode = options.clang_preprocessor_mode,
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.verbose_cc = options.verbose_cc,
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.verbose_air = options.verbose_air,
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.verbose_mir = options.verbose_mir,
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.verbose_llvm_ir = options.verbose_llvm_ir,
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.verbose_cimport = options.verbose_cimport,
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.verbose_llvm_cpu_features = options.verbose_llvm_cpu_features,
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@ -319,6 +319,14 @@ pub fn generate(
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else => |e| return e,
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};
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if (builtin.mode == .Debug and bin_file.options.module.?.comp.verbose_mir) {
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const w = std.io.getStdErr().writer();
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w.print("# Begin Function MIR: {s}:\n", .{module_fn.owner_decl.name}) catch {};
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const print = @import("./PrintMir.zig"){ .mir = mir };
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print.printMir(w) catch {}; // we don't care if the debug printing fails
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w.print("# End Function MIR: {s}:\n\n", .{module_fn.owner_decl.name}) catch {};
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}
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if (function.err_msg) |em| {
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return FnResult{ .fail = em };
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} else {
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579
src/arch/x86_64/PrintMir.zig
Normal file
579
src/arch/x86_64/PrintMir.zig
Normal file
@ -0,0 +1,579 @@
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//! This file contains the functionality for print x86_64 MIR in a debug way, interleaved with AIR
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const Print = @This();
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const std = @import("std");
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const assert = std.debug.assert;
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const bits = @import("bits.zig");
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const leb128 = std.leb;
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const link = @import("../../link.zig");
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const log = std.log.scoped(.codegen);
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const math = std.math;
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const mem = std.mem;
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const Air = @import("../../Air.zig");
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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const DW = std.dwarf;
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const Encoder = bits.Encoder;
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const ErrorMsg = Module.ErrorMsg;
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const MCValue = @import("CodeGen.zig").MCValue;
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const Mir = @import("Mir.zig");
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const Module = @import("../../Module.zig");
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const Instruction = bits.Instruction;
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const Register = bits.Register;
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const Type = @import("../../type.zig").Type;
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const fmtIntSizeBin = std.fmt.fmtIntSizeBin;
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mir: Mir,
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pub fn printMir(print: *const Print, w: anytype) !void {
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const instruction_bytes = print.mir.instructions.len *
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// Here we don't use @sizeOf(Mir.Inst.Data) because it would include
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// the debug safety tag but we want to measure release size.
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(@sizeOf(Mir.Inst.Tag) + 2 + 8);
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const extra_bytes = print.mir.extra.len * @sizeOf(u32);
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const total_bytes = @sizeOf(Mir) + instruction_bytes + extra_bytes;
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// zig fmt: off
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std.debug.print(
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\\# Total MIR bytes: {}
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\\# MIR Instructions: {d} ({})
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\\# MIR Extra Data: {d} ({})
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\\
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, .{
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fmtIntSizeBin(total_bytes),
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print.mir.instructions.len, fmtIntSizeBin(instruction_bytes),
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print.mir.extra.len, fmtIntSizeBin(extra_bytes),
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});
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// zig fmt: on
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const mir_tags = print.mir.instructions.items(.tag);
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for (mir_tags) |tag, index| {
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try w.writeAll(" ");
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const inst = @intCast(u32, index);
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switch (tag) {
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.adc => try print.mirArith(.adc, inst, w),
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.add => try print.mirArith(.add, inst, w),
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.sub => try print.mirArith(.sub, inst, w),
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.xor => try print.mirArith(.xor, inst, w),
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.@"and" => try print.mirArith(.@"and", inst, w),
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.@"or" => try print.mirArith(.@"or", inst, w),
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.sbb => try print.mirArith(.sbb, inst, w),
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.cmp => try print.mirArith(.cmp, inst, w),
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.adc_scale_src => try print.mirArithScaleSrc(.adc, inst, w),
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.add_scale_src => try print.mirArithScaleSrc(.add, inst, w),
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.sub_scale_src => try print.mirArithScaleSrc(.sub, inst, w),
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.xor_scale_src => try print.mirArithScaleSrc(.xor, inst, w),
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.and_scale_src => try print.mirArithScaleSrc(.@"and", inst, w),
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.or_scale_src => try print.mirArithScaleSrc(.@"or", inst, w),
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.sbb_scale_src => try print.mirArithScaleSrc(.sbb, inst, w),
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.cmp_scale_src => try print.mirArithScaleSrc(.cmp, inst, w),
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.adc_scale_dst => try print.mirArithScaleDst(.adc, inst, w),
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.add_scale_dst => try print.mirArithScaleDst(.add, inst, w),
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.sub_scale_dst => try print.mirArithScaleDst(.sub, inst, w),
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.xor_scale_dst => try print.mirArithScaleDst(.xor, inst, w),
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.and_scale_dst => try print.mirArithScaleDst(.@"and", inst, w),
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.or_scale_dst => try print.mirArithScaleDst(.@"or", inst, w),
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.sbb_scale_dst => try print.mirArithScaleDst(.sbb, inst, w),
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.cmp_scale_dst => try print.mirArithScaleDst(.cmp, inst, w),
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.adc_scale_imm => try print.mirArithScaleImm(.adc, inst, w),
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.add_scale_imm => try print.mirArithScaleImm(.add, inst, w),
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.sub_scale_imm => try print.mirArithScaleImm(.sub, inst, w),
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.xor_scale_imm => try print.mirArithScaleImm(.xor, inst, w),
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.and_scale_imm => try print.mirArithScaleImm(.@"and", inst, w),
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.or_scale_imm => try print.mirArithScaleImm(.@"or", inst, w),
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.sbb_scale_imm => try print.mirArithScaleImm(.sbb, inst, w),
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.cmp_scale_imm => try print.mirArithScaleImm(.cmp, inst, w),
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.mov => try print.mirArith(.mov, inst, w),
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.mov_scale_src => try print.mirArithScaleSrc(.mov, inst, w),
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.mov_scale_dst => try print.mirArithScaleDst(.mov, inst, w),
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.mov_scale_imm => try print.mirArithScaleImm(.mov, inst, w),
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.movabs => try print.mirMovabs(inst, w),
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.lea => try print.mirLea(inst, w),
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.lea_rip => try print.mirLeaRip(inst, w),
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.imul_complex => try print.mirIMulComplex(inst, w),
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.push => try print.mirPushPop(.push, inst, w),
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.pop => try print.mirPushPop(.pop, inst, w),
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.jmp => try print.mirJmpCall(.jmp, inst, w),
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.call => try print.mirJmpCall(.call, inst, w),
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// .cond_jmp_greater_less => try print.mirCondJmp(.cond_jmp_greater_less, inst, w),
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// .cond_jmp_above_below => try print.mirCondJmp(.cond_jmp_above_below, inst, w),
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// .cond_jmp_eq_ne => try print.mirCondJmp(.cond_jmp_eq_ne, inst, w),
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// .cond_set_byte_greater_less => try print.mirCondSetByte(.cond_set_byte_greater_less, inst, w),
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// .cond_set_byte_above_below => try print.mirCondSetByte(.cond_set_byte_above_below, inst, w),
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// .cond_set_byte_eq_ne => try print.mirCondSetByte(.cond_set_byte_eq_ne, inst, w),
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// .@"test" => try print.mirTest(inst, w),
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.brk => try w.writeAll("brk\n"),
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.ret => try w.writeAll("ret\n"),
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.nop => try w.writeAll("nop\n"),
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.syscall => try w.writeAll("syscall\n"),
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.call_extern => try print.mirCallExtern(inst, w),
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.dbg_line, .dbg_prologue_end, .dbg_epilogue_begin, .arg_dbg_info => try w.print("{s}\n", .{@tagName(tag)}),
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.push_regs_from_callee_preserved_regs => try print.mirPushPopRegsFromCalleePreservedRegs(.push, inst, w),
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.pop_regs_from_callee_preserved_regs => try print.mirPushPopRegsFromCalleePreservedRegs(.pop, inst, w),
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else => {
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try w.print("TODO emit asm for {s}\n", .{@tagName(tag)});
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},
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}
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}
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}
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fn mirPushPop(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
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const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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// PUSH/POP reg
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try w.print("{s} {s}", .{ @tagName(tag), @tagName(ops.reg1) });
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},
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0b01 => {
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// PUSH/POP r/m64
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const imm = print.mir.instructions.items(.data)[inst].imm;
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try w.print("{s} [{s} + {d}]", .{ @tagName(tag), @tagName(ops.reg1), imm });
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},
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0b10 => {
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const imm = print.mir.instructions.items(.data)[inst].imm;
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// PUSH imm32
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assert(tag == .push);
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try w.print("{s} {d}", .{ @tagName(tag), imm });
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},
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0b11 => unreachable,
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}
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try w.writeByte('\n');
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}
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fn mirPushPopRegsFromCalleePreservedRegs(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
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const callee_preserved_regs = bits.callee_preserved_regs;
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// PUSH/POP reg
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const regs = print.mir.instructions.items(.data)[inst].regs_to_push_or_pop;
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if (regs == 0) return w.writeAll("push/pop no regs from callee_preserved_regs\n");
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if (tag == .push) {
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try w.writeAll("push ");
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for (callee_preserved_regs) |reg, i| {
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if ((regs >> @intCast(u5, i)) & 1 == 0) continue;
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try w.print("{s}, ", .{@tagName(reg)});
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}
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} else {
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// pop in the reverse direction
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var i = callee_preserved_regs.len;
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try w.writeAll("pop ");
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while (i > 0) : (i -= 1) {
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if ((regs >> @intCast(u5, i - 1)) & 1 == 0) continue;
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const reg = callee_preserved_regs[i - 1];
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try w.print("{s}, ", .{@tagName(reg)});
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}
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}
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try w.writeByte('\n');
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}
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fn mirJmpCall(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
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try w.print("{s} ", .{@tagName(tag)});
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const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
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const flag = @truncate(u1, ops.flags);
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if (flag == 0) {
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return w.writeAll("TODO target\n");
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}
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if (ops.reg1 == .none) {
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// JMP/CALL [imm]
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const imm = print.mir.instructions.items(.data)[inst].imm;
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try w.print("[{x}]\n", .{imm});
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return;
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}
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// JMP/CALL reg
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try w.print("{s}\n", .{@tagName(ops.reg1)});
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}
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const CondType = enum {
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/// greater than or equal
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gte,
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/// greater than
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gt,
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/// less than
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lt,
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/// less than or equal
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lte,
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/// above or equal
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ae,
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/// above
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a,
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/// below
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b,
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/// below or equal
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be,
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/// not equal
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ne,
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/// equal
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eq,
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fn fromTagAndFlags(tag: Mir.Inst.Tag, flags: u2) CondType {
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return switch (tag) {
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.cond_jmp_greater_less,
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.cond_set_byte_greater_less,
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=> switch (flags) {
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0b00 => CondType.gte,
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0b01 => CondType.gt,
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0b10 => CondType.lt,
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0b11 => CondType.lte,
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},
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.cond_jmp_above_below,
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.cond_set_byte_above_below,
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=> switch (flags) {
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0b00 => CondType.ae,
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0b01 => CondType.a,
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0b10 => CondType.b,
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0b11 => CondType.be,
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},
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.cond_jmp_eq_ne,
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.cond_set_byte_eq_ne,
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=> switch (@truncate(u1, flags)) {
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0b0 => CondType.ne,
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0b1 => CondType.eq,
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},
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else => unreachable,
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};
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}
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};
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inline fn getCondOpCode(tag: Mir.Inst.Tag, cond: CondType) u8 {
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switch (cond) {
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.gte => return switch (tag) {
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.cond_jmp_greater_less => 0x8d,
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.cond_set_byte_greater_less => 0x9d,
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else => unreachable,
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},
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.gt => return switch (tag) {
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.cond_jmp_greater_less => 0x8f,
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.cond_set_byte_greater_less => 0x9f,
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else => unreachable,
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},
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.lt => return switch (tag) {
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.cond_jmp_greater_less => 0x8c,
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.cond_set_byte_greater_less => 0x9c,
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else => unreachable,
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},
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.lte => return switch (tag) {
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.cond_jmp_greater_less => 0x8e,
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.cond_set_byte_greater_less => 0x9e,
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else => unreachable,
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},
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.ae => return switch (tag) {
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.cond_jmp_above_below => 0x83,
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.cond_set_byte_above_below => 0x93,
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else => unreachable,
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},
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.a => return switch (tag) {
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.cond_jmp_above_below => 0x87,
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.cond_set_byte_greater_less => 0x97,
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else => unreachable,
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},
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.b => return switch (tag) {
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.cond_jmp_above_below => 0x82,
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.cond_set_byte_greater_less => 0x92,
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else => unreachable,
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},
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.be => return switch (tag) {
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.cond_jmp_above_below => 0x86,
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.cond_set_byte_greater_less => 0x96,
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else => unreachable,
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},
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.eq => return switch (tag) {
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.cond_jmp_eq_ne => 0x84,
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.cond_set_byte_eq_ne => 0x94,
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else => unreachable,
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},
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.ne => return switch (tag) {
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.cond_jmp_eq_ne => 0x85,
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.cond_set_byte_eq_ne => 0x95,
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else => unreachable,
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},
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}
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}
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fn mirCondJmp(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
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_ = w; // TODO
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const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
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const target = print.mir.instructions.items(.data)[inst].inst;
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const cond = CondType.fromTagAndFlags(tag, ops.flags);
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const opc = getCondOpCode(tag, cond);
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const source = print.code.items.len;
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const encoder = try Encoder.init(print.code, 6);
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encoder.opcode_2byte(0x0f, opc);
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try print.relocs.append(print.bin_file.allocator, .{
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.source = source,
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.target = target,
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.offset = print.code.items.len,
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.length = 6,
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});
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encoder.imm32(0);
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}
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fn mirCondSetByte(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
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_ = w; // TODO
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const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
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const cond = CondType.fromTagAndFlags(tag, ops.flags);
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const opc = getCondOpCode(tag, cond);
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const encoder = try Encoder.init(print.code, 4);
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encoder.rex(.{
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.w = true,
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.b = ops.reg1.isExtended(),
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});
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encoder.opcode_2byte(0x0f, opc);
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encoder.modRm_direct(0x0, ops.reg1.lowId());
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}
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fn mirTest(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
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_ = w; // TODO
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const tag = print.mir.instructions.items(.tag)[inst];
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assert(tag == .@"test");
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const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => blk: {
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if (ops.reg2 == .none) {
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// TEST r/m64, imm32
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const imm = print.mir.instructions.items(.data)[inst].imm;
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if (ops.reg1.to64() == .rax) {
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// TODO reduce the size of the instruction if the immediate
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// is smaller than 32 bits
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const encoder = try Encoder.init(print.code, 6);
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encoder.rex(.{
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.w = true,
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});
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encoder.opcode_1byte(0xa9);
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encoder.imm32(imm);
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break :blk;
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}
|
||||
const opc: u8 = if (ops.reg1.size() == 8) 0xf6 else 0xf7;
|
||||
const encoder = try Encoder.init(print.code, 7);
|
||||
encoder.rex(.{
|
||||
.w = true,
|
||||
.b = ops.reg1.isExtended(),
|
||||
});
|
||||
encoder.opcode_1byte(opc);
|
||||
encoder.modRm_direct(0, ops.reg1.lowId());
|
||||
encoder.imm8(@intCast(i8, imm));
|
||||
break :blk;
|
||||
}
|
||||
// TEST r/m64, r64
|
||||
return print.fail("TODO TEST r/m64, r64", .{});
|
||||
},
|
||||
else => return print.fail("TODO more TEST alternatives", .{}),
|
||||
}
|
||||
}
|
||||
|
||||
const EncType = enum {
|
||||
/// OP r/m64, imm32
|
||||
mi,
|
||||
|
||||
/// OP r/m64, r64
|
||||
mr,
|
||||
|
||||
/// OP r64, r/m64
|
||||
rm,
|
||||
};
|
||||
|
||||
const OpCode = struct {
|
||||
opc: u8,
|
||||
/// Only used if `EncType == .mi`.
|
||||
modrm_ext: u3,
|
||||
};
|
||||
|
||||
inline fn getArithOpCode(tag: Mir.Inst.Tag, enc: EncType) OpCode {
|
||||
switch (enc) {
|
||||
.mi => return switch (tag) {
|
||||
.adc => .{ .opc = 0x81, .modrm_ext = 0x2 },
|
||||
.add => .{ .opc = 0x81, .modrm_ext = 0x0 },
|
||||
.sub => .{ .opc = 0x81, .modrm_ext = 0x5 },
|
||||
.xor => .{ .opc = 0x81, .modrm_ext = 0x6 },
|
||||
.@"and" => .{ .opc = 0x81, .modrm_ext = 0x4 },
|
||||
.@"or" => .{ .opc = 0x81, .modrm_ext = 0x1 },
|
||||
.sbb => .{ .opc = 0x81, .modrm_ext = 0x3 },
|
||||
.cmp => .{ .opc = 0x81, .modrm_ext = 0x7 },
|
||||
.mov => .{ .opc = 0xc7, .modrm_ext = 0x0 },
|
||||
else => unreachable,
|
||||
},
|
||||
.mr => {
|
||||
const opc: u8 = switch (tag) {
|
||||
.adc => 0x11,
|
||||
.add => 0x01,
|
||||
.sub => 0x29,
|
||||
.xor => 0x31,
|
||||
.@"and" => 0x21,
|
||||
.@"or" => 0x09,
|
||||
.sbb => 0x19,
|
||||
.cmp => 0x39,
|
||||
.mov => 0x89,
|
||||
else => unreachable,
|
||||
};
|
||||
return .{ .opc = opc, .modrm_ext = undefined };
|
||||
},
|
||||
.rm => {
|
||||
const opc: u8 = switch (tag) {
|
||||
.adc => 0x13,
|
||||
.add => 0x03,
|
||||
.sub => 0x2b,
|
||||
.xor => 0x33,
|
||||
.@"and" => 0x23,
|
||||
.@"or" => 0x0b,
|
||||
.sbb => 0x1b,
|
||||
.cmp => 0x3b,
|
||||
.mov => 0x8b,
|
||||
else => unreachable,
|
||||
};
|
||||
return .{ .opc = opc, .modrm_ext = undefined };
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
fn mirArith(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
try w.writeAll(@tagName(tag));
|
||||
try w.writeByte(' ');
|
||||
switch (ops.flags) {
|
||||
0b00 => {
|
||||
if (ops.reg2 == .none) {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
try w.print("{s}, {d}", .{ @tagName(ops.reg1), imm });
|
||||
} else try w.print("{s}, {s}", .{ @tagName(ops.reg1), @tagName(ops.reg2) });
|
||||
},
|
||||
0b01 => {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.reg2 == .none) {
|
||||
try w.print("{s}, [ds:{d}]", .{ @tagName(ops.reg1), imm });
|
||||
} else {
|
||||
try w.print("{s}, [{s} + {d}]", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm });
|
||||
}
|
||||
},
|
||||
0b10 => {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.reg2 == .none) {
|
||||
try w.print("[{s} + 0], {d}", .{ @tagName(ops.reg1), imm });
|
||||
} else {
|
||||
try w.print("[{s} + {d}], {s}", .{ @tagName(ops.reg1), imm, @tagName(ops.reg2) });
|
||||
}
|
||||
},
|
||||
0b11 => {
|
||||
if (ops.reg2 == .none) {
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
|
||||
try w.print("[{s} + {d}], {d}", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand });
|
||||
}
|
||||
try w.writeAll("TODO");
|
||||
},
|
||||
}
|
||||
try w.writeByte('\n');
|
||||
}
|
||||
|
||||
fn mirArithScaleSrc(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const scale = ops.flags;
|
||||
// OP reg1, [reg2 + scale*rcx + imm32]
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
try w.print("{s} {s}, [{s} + {d}*rcx + {d}]\n", .{ @tagName(tag), @tagName(ops.reg1), @tagName(ops.reg2), scale, imm });
|
||||
}
|
||||
|
||||
fn mirArithScaleDst(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const scale = ops.flags;
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
|
||||
if (ops.reg2 == .none) {
|
||||
// OP [reg1 + scale*rax + 0], imm32
|
||||
try w.print("{s} [{s} + {d}*rcx + 0], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm });
|
||||
}
|
||||
|
||||
// OP [reg1 + scale*rax + imm32], reg2
|
||||
try w.print("{s} [{s} + {d}*rcx + {d}], {s}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm, @tagName(ops.reg2) });
|
||||
}
|
||||
|
||||
fn mirArithScaleImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const scale = ops.flags;
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
|
||||
try w.print("{s} [{s} + {d}*rcx + {d}], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm_pair.dest_off, imm_pair.operand });
|
||||
}
|
||||
|
||||
fn mirMovabs(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const tag = print.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .movabs);
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
|
||||
const is_64 = ops.reg1.size() == 64;
|
||||
const imm: i128 = if (is_64) blk: {
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm64 = print.mir.extraData(Mir.Imm64, payload).data;
|
||||
break :blk imm64.decode();
|
||||
} else print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.flags == 0b00) {
|
||||
// movabs reg, imm64
|
||||
try w.print("movabs {s}, {d}\n", .{ @tagName(ops.reg1), imm });
|
||||
}
|
||||
if (ops.reg1 == .none) {
|
||||
try w.writeAll("movabs moffs64, rax\n");
|
||||
} else {
|
||||
// movabs rax, moffs64
|
||||
try w.writeAll("movabs rax, moffs64\n");
|
||||
}
|
||||
}
|
||||
|
||||
fn mirIMulComplex(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const tag = print.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .imul_complex);
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
switch (ops.flags) {
|
||||
0b00 => {
|
||||
try w.print("imul {s}, {s}\n", .{ @tagName(ops.reg1), @tagName(ops.reg2) });
|
||||
},
|
||||
0b10 => {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
try w.print("imul {s}, {s}, {d}\n", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm });
|
||||
},
|
||||
else => return w.writeAll("TODO implement imul\n"),
|
||||
}
|
||||
}
|
||||
|
||||
fn mirLea(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const tag = print.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .lea);
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
assert(ops.flags == 0b01);
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
|
||||
try w.print("lea {s} [{s} + {d}]\n", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm });
|
||||
}
|
||||
|
||||
fn mirLeaRip(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
_ = print;
|
||||
_ = inst;
|
||||
return w.writeAll("TODO lea_rip\n");
|
||||
}
|
||||
|
||||
fn mirCallExtern(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
_ = print;
|
||||
_ = inst;
|
||||
return w.writeAll("TODO call_extern");
|
||||
}
|
||||
@ -448,6 +448,7 @@ const usage_build_generic =
|
||||
\\ --verbose-link Display linker invocations
|
||||
\\ --verbose-cc Display C compiler invocations
|
||||
\\ --verbose-air Enable compiler debug output for Zig AIR
|
||||
\\ --verbose-mir Enable compiler debug output for Zig MIR
|
||||
\\ --verbose-llvm-ir Enable compiler debug output for LLVM IR
|
||||
\\ --verbose-cimport Enable compiler debug output for C imports
|
||||
\\ --verbose-llvm-cpu-features Enable compiler debug output for LLVM CPU features
|
||||
@ -575,6 +576,7 @@ fn buildOutputType(
|
||||
var verbose_link = std.process.hasEnvVarConstant("ZIG_VERBOSE_LINK");
|
||||
var verbose_cc = std.process.hasEnvVarConstant("ZIG_VERBOSE_CC");
|
||||
var verbose_air = false;
|
||||
var verbose_mir = false;
|
||||
var verbose_llvm_ir = false;
|
||||
var verbose_cimport = false;
|
||||
var verbose_llvm_cpu_features = false;
|
||||
@ -1170,6 +1172,8 @@ fn buildOutputType(
|
||||
verbose_cc = true;
|
||||
} else if (mem.eql(u8, arg, "--verbose-air")) {
|
||||
verbose_air = true;
|
||||
} else if (mem.eql(u8, arg, "--verbose-mir")) {
|
||||
verbose_mir = true;
|
||||
} else if (mem.eql(u8, arg, "--verbose-llvm-ir")) {
|
||||
verbose_llvm_ir = true;
|
||||
} else if (mem.eql(u8, arg, "--verbose-cimport")) {
|
||||
@ -2333,6 +2337,7 @@ fn buildOutputType(
|
||||
.verbose_cc = verbose_cc,
|
||||
.verbose_link = verbose_link,
|
||||
.verbose_air = verbose_air,
|
||||
.verbose_mir = verbose_mir,
|
||||
.verbose_llvm_ir = verbose_llvm_ir,
|
||||
.verbose_cimport = verbose_cimport,
|
||||
.verbose_llvm_cpu_features = verbose_llvm_cpu_features,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user