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Merge pull request #25437 from alexrp/std-debug
`std.debug`: LoongArch and RISC-V unwind support + some minor cleanups
This commit is contained in:
Alex Rønne Petersen
GitHub
commit
bc4da9a907
@ -61,28 +61,12 @@ pub const cpu_context = @import("debug/cpu_context.zig");
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/// ```
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pub const SelfInfo = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "SelfInfo"))
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root.debug.SelfInfo
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else switch (native_os) {
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.linux,
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.netbsd,
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.freebsd,
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.dragonfly,
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.openbsd,
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.solaris,
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.illumos,
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=> @import("debug/SelfInfo/Elf.zig"),
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.macos,
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.ios,
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.watchos,
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.tvos,
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.visionos,
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=> @import("debug/SelfInfo/Darwin.zig"),
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.uefi,
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.windows,
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=> @import("debug/SelfInfo/Windows.zig"),
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else => void,
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else switch (std.Target.ObjectFormat.default(native_os, native_arch)) {
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.coff => if (native_os == .windows) @import("debug/SelfInfo/Windows.zig") else void,
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.elf => @import("debug/SelfInfo/Elf.zig"),
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.macho => @import("debug/SelfInfo/MachO.zig"),
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.goff, .plan9, .spirv, .wasm, .xcoff => void,
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.c, .hex, .raw => unreachable,
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};
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pub const SelfInfoError = error{
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@ -1429,30 +1429,36 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
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/// Returns `null` for CPU architectures without an instruction pointer register.
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pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
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return switch (arch) {
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.aarch64, .aarch64_be => 32,
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.arm, .armeb, .thumb, .thumbeb => 15,
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.loongarch32, .loongarch64 => 32,
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.riscv32, .riscv32be, .riscv64, .riscv64be => 32,
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.x86 => 8,
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.x86_64 => 16,
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.arm, .armeb, .thumb, .thumbeb => 15,
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.aarch64, .aarch64_be => 32,
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else => null,
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};
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}
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pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
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return switch (arch) {
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.aarch64, .aarch64_be => 29,
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.arm, .armeb, .thumb, .thumbeb => 11,
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.loongarch32, .loongarch64 => 22,
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.riscv32, .riscv32be, .riscv64, .riscv64be => 8,
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.x86 => 5,
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.x86_64 => 6,
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.arm, .armeb, .thumb, .thumbeb => 11,
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.aarch64, .aarch64_be => 29,
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else => unreachable,
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};
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}
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pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
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return switch (arch) {
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.aarch64, .aarch64_be => 31,
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.arm, .armeb, .thumb, .thumbeb => 13,
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.loongarch32, .loongarch64 => 3,
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.riscv32, .riscv32be, .riscv64, .riscv64be => 2,
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.x86 => 4,
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.x86_64 => 7,
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.arm, .armeb, .thumb, .thumbeb => 13,
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.aarch64, .aarch64_be => 31,
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else => unreachable,
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};
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}
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@ -1470,10 +1476,6 @@ pub fn supportsUnwinding(target: *const std.Target) bool {
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.spirv64,
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=> false,
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// Enabling this causes relocation errors such as:
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// error: invalid relocation type R_RISCV_SUB32 at offset 0x20
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.riscv64, .riscv64be, .riscv32, .riscv32be => false,
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// Conservative guess. Feel free to update this logic with any targets
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// that are known to not support Dwarf unwinding.
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else => true,
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@ -256,7 +256,18 @@ fn evalInstructions(
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.offset = cfa.offset_sf * cie.data_alignment_factor,
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} },
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.def_cfa_reg => |register| switch (vm.current_row.cfa) {
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.none, .expression => return error.InvalidOperation,
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.none => {
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// According to the DWARF specification, this is not valid, because this
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// instruction can only be used to replace the register if the rule is already a
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// `.reg_off`. However, this is emitted in practice by GNU toolchains for some
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// targets, and so by convention is interpreted as equivalent to `.def_cfa` with
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// an offset of 0.
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vm.current_row.cfa = .{ .reg_off = .{
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.register = register,
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.offset = 0,
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} };
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},
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.expression => return error.InvalidOperation,
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.reg_off => |*ro| ro.register = register,
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},
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.def_cfa_offset => |offset| switch (vm.current_row.cfa) {
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@ -84,12 +84,35 @@ pub const can_unwind: bool = s: {
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// Notably, we are yet to support unwinding on ARM. There, unwinding is not done through
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// `.eh_frame`, but instead with the `.ARM.exidx` section, which has a different format.
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const archs: []const std.Target.Cpu.Arch = switch (builtin.target.os.tag) {
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.linux => &.{ .x86, .x86_64, .aarch64, .aarch64_be },
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.netbsd => &.{ .x86, .x86_64, .aarch64, .aarch64_be },
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.freebsd => &.{ .x86_64, .aarch64, .aarch64_be },
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.openbsd => &.{.x86_64},
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.solaris => &.{ .x86, .x86_64 },
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.illumos => &.{ .x86, .x86_64 },
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.linux => &.{
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.aarch64,
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.aarch64_be,
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.loongarch64,
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.riscv32,
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.riscv64,
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.x86,
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.x86_64,
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},
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.netbsd => &.{
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.aarch64,
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.aarch64_be,
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.x86,
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.x86_64,
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},
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.freebsd => &.{
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.x86_64,
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.aarch64,
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},
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.openbsd => &.{
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.x86_64,
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},
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.solaris => &.{
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.x86_64,
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},
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.illumos => &.{
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.x86,
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.x86_64,
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},
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else => unreachable,
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};
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for (archs) |a| {
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@ -371,7 +371,7 @@ fn unwindFrameInner(si: *SelfInfo, gpa: Allocator, context: *UnwindContext) !usi
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return context.next(gpa, &rules);
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},
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},
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.aarch64, .aarch64_be => switch (encoding.mode.arm64) {
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.aarch64 => switch (encoding.mode.arm64) {
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.OLD => return error.UnsupportedDebugInfo,
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.FRAMELESS => ip: {
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const sp = (try dwarfRegNative(&context.cpu_state, sp_reg_num)).*;
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@ -88,7 +88,7 @@ pub const UnwindContext = struct {
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.R15 = ctx.gprs.get(.r15),
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.Rip = ctx.gprs.get(.rip),
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}),
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.aarch64, .aarch64_be => .{
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.aarch64 => .{
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.ContextFlags = 0,
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.Cpsr = 0,
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.DUMMYUNIONNAME = .{ .X = ctx.x },
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@ -4,10 +4,12 @@
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pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuContext"))
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root.debug.CpuContext
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else switch (native_arch) {
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.aarch64, .aarch64_be => Aarch64,
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.arm, .armeb, .thumb, .thumbeb => Arm,
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.loongarch32, .loongarch64 => LoongArch,
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.riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,
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.x86 => X86,
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.x86_64 => X86_64,
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.arm, .armeb, .thumb, .thumbeb => Arm,
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.aarch64, .aarch64_be => Aarch64,
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else => noreturn,
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};
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@ -21,7 +23,7 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
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const uc: *const signal_ucontext_t = @ptrCast(@alignCast(ctx_ptr));
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return switch (native_arch) {
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.x86 => switch (native_os) {
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.linux, .netbsd, .solaris, .illumos => .{ .gprs = .init(.{
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.linux, .netbsd, .illumos => .{ .gprs = .init(.{
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.eax = uc.mcontext.gregs[std.posix.REG.EAX],
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.ecx = uc.mcontext.gregs[std.posix.REG.ECX],
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.edx = uc.mcontext.gregs[std.posix.REG.EDX],
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@ -92,7 +94,7 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
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.r15 = @bitCast(uc.sc_r15),
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.rip = @bitCast(uc.sc_rip),
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}) },
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.macos, .ios => .{ .gprs = .init(.{
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.driverkit, .macos, .ios => .{ .gprs = .init(.{
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.rax = uc.mcontext.ss.rax,
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.rdx = uc.mcontext.ss.rdx,
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.rcx = uc.mcontext.ss.rcx,
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@ -137,7 +139,7 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
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else => null,
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},
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.aarch64, .aarch64_be => switch (builtin.os.tag) {
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.macos, .ios, .tvos, .watchos, .visionos => .{
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.driverkit, .macos, .ios, .tvos, .watchos, .visionos => .{
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.x = uc.mcontext.ss.regs ++ @as([2]u64, .{
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uc.mcontext.ss.fp, // x29 = fp
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uc.mcontext.ss.lr, // x30 = lr
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@ -173,6 +175,20 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
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},
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else => null,
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},
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.loongarch64 => switch (builtin.os.tag) {
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.linux => .{
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.r = uc.mcontext.regs, // includes r0 (hardwired zero)
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.pc = uc.mcontext.pc,
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},
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else => null,
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},
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.riscv32, .riscv64 => switch (builtin.os.tag) {
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.linux => .{
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.r = [1]usize{0} ++ uc.mcontext.gregs[1..].*, // r0 position is used for pc; replace with zero
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.pc = uc.mcontext.gregs[0],
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},
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else => null,
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},
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else => null,
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};
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}
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@ -209,7 +225,7 @@ pub fn fromWindowsContext(ctx: *const std.os.windows.CONTEXT) Native {
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.r15 = ctx.R15,
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.rip = ctx.Rip,
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}) },
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.aarch64, .aarch64_be => .{
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.aarch64 => .{
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.x = ctx.DUMMYUNIONNAME.X[0..31].*,
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.sp = ctx.Sp,
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.pc = ctx.Pc,
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@ -371,7 +387,6 @@ pub const Arm = struct {
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pub fn dwarfRegisterBytes(ctx: *Arm, register_num: u16) DwarfRegisterError![]u8 {
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// DWARF for the Arm(r) Architecture § 4.1 "DWARF register names"
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switch (register_num) {
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// The order of `Gpr` intentionally matches DWARF's mappings.
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0...15 => return @ptrCast(&ctx.r[register_num]),
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64...95 => return error.UnsupportedRegister, // S0 - S31
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@ -444,7 +459,6 @@ pub const Aarch64 = extern struct {
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pub fn dwarfRegisterBytes(ctx: *Aarch64, register_num: u16) DwarfRegisterError![]u8 {
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// DWARF for the Arm(r) 64-bit Architecture (AArch64) § 4.1 "DWARF register names"
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switch (register_num) {
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// The order of `Gpr` intentionally matches DWARF's mappings.
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0...30 => return @ptrCast(&ctx.x[register_num]),
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31 => return @ptrCast(&ctx.sp),
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32 => return @ptrCast(&ctx.pc),
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@ -467,11 +481,207 @@ pub const Aarch64 = extern struct {
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}
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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pub const LoongArch = extern struct {
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/// The numbered general-purpose registers r0 - r31. r0 must be zero.
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r: [32]usize,
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pc: usize,
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pub inline fn current() LoongArch {
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var ctx: LoongArch = undefined;
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asm volatile (if (@sizeOf(usize) == 8)
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\\ st.d $zero, $t0, 0
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\\ st.d $ra, $t0, 8
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\\ st.d $tp, $t0, 16
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\\ st.d $sp, $t0, 24
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\\ st.d $a0, $t0, 32
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\\ st.d $a1, $t0, 40
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\\ st.d $a2, $t0, 48
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\\ st.d $a3, $t0, 56
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\\ st.d $a4, $t0, 64
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\\ st.d $a5, $t0, 72
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\\ st.d $a6, $t0, 80
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\\ st.d $a7, $t0, 88
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\\ st.d $t0, $t0, 96
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\\ st.d $t1, $t0, 104
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\\ st.d $t2, $t0, 112
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\\ st.d $t3, $t0, 120
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\\ st.d $t4, $t0, 128
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\\ st.d $t5, $t0, 136
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\\ st.d $t6, $t0, 144
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\\ st.d $t7, $t0, 152
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\\ st.d $t8, $t0, 160
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\\ st.d $r21, $t0, 168
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\\ st.d $fp, $t0, 176
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\\ st.d $s0, $t0, 184
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\\ st.d $s1, $t0, 192
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\\ st.d $s2, $t0, 200
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\\ st.d $s3, $t0, 208
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\\ st.d $s4, $t0, 216
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\\ st.d $s5, $t0, 224
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\\ st.d $s6, $t0, 232
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\\ st.d $s7, $t0, 240
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\\ st.d $s8, $t0, 248
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\\ bl 1f
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\\1:
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\\ st.d $ra, $t0, 256
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\\ ld.d $ra, $t0, 8
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else
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\\ st.w $zero, $t0, 0
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\\ st.w $ra, $t0, 4
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\\ st.w $tp, $t0, 8
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\\ st.w $sp, $t0, 12
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\\ st.w $a0, $t0, 16
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\\ st.w $a1, $t0, 20
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\\ st.w $a2, $t0, 24
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\\ st.w $a3, $t0, 28
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\\ st.w $a4, $t0, 32
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\\ st.w $a5, $t0, 36
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\\ st.w $a6, $t0, 40
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\\ st.w $a7, $t0, 44
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\\ st.w $t0, $t0, 48
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\\ st.w $t1, $t0, 52
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\\ st.w $t2, $t0, 56
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\\ st.w $t3, $t0, 60
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\\ st.w $t4, $t0, 64
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\\ st.w $t5, $t0, 68
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\\ st.w $t6, $t0, 72
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\\ st.w $t7, $t0, 76
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\\ st.w $t8, $t0, 80
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\\ st.w $r21, $t0, 84
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\\ st.w $fp, $t0, 88
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\\ st.w $s0, $t0, 92
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\\ st.w $s1, $t0, 96
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\\ st.w $s2, $t0, 100
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\\ st.w $s3, $t0, 104
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\\ st.w $s4, $t0, 108
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\\ st.w $s5, $t0, 112
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\\ st.w $s6, $t0, 116
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\\ st.w $s7, $t0, 120
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\\ st.w $s8, $t0, 124
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\\ bl 1f
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\\1:
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\\ st.w $ra, $t0, 128
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\\ ld.w $ra, $t0, 4
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:
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: [gprs] "{$r12}" (&ctx),
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: .{ .memory = true });
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return ctx;
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}
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pub fn dwarfRegisterBytes(ctx: *LoongArch, register_num: u16) DwarfRegisterError![]u8 {
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switch (register_num) {
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0...31 => return @ptrCast(&ctx.r[register_num]),
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32 => return @ptrCast(&ctx.pc),
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else => return error.InvalidRegister,
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}
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}
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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pub const Riscv = extern struct {
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/// The numbered general-purpose registers r0 - r31. r0 must be zero.
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r: [32]usize,
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pc: usize,
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pub inline fn current() Riscv {
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var ctx: Riscv = undefined;
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asm volatile (if (@sizeOf(usize) == 8)
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\\ sd zero, 0(t0)
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\\ sd ra, 8(t0)
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\\ sd sp, 16(t0)
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\\ sd gp, 24(t0)
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\\ sd tp, 32(t0)
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\\ sd t0, 40(t0)
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\\ sd t1, 48(t0)
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\\ sd t2, 56(t0)
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\\ sd s0, 64(t0)
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\\ sd s1, 72(t0)
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\\ sd a0, 80(t0)
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\\ sd a1, 88(t0)
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\\ sd a2, 96(t0)
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\\ sd a3, 104(t0)
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\\ sd a4, 112(t0)
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\\ sd a5, 120(t0)
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\\ sd a6, 128(t0)
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\\ sd a7, 136(t0)
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\\ sd s2, 144(t0)
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\\ sd s3, 152(t0)
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\\ sd s4, 160(t0)
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\\ sd s5, 168(t0)
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\\ sd s6, 176(t0)
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\\ sd s7, 184(t0)
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\\ sd s8, 192(t0)
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\\ sd s9, 200(t0)
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\\ sd s10, 208(t0)
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\\ sd s11, 216(t0)
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\\ sd t3, 224(t0)
|
||||
\\ sd t4, 232(t0)
|
||||
\\ sd t5, 240(t0)
|
||||
\\ sd t6, 248(t0)
|
||||
\\ jal ra, 1f
|
||||
\\1:
|
||||
\\ sd ra, 256(t0)
|
||||
\\ ld ra, 8(t0)
|
||||
else
|
||||
\\ sw zero, 0(t0)
|
||||
\\ sw ra, 4(t0)
|
||||
\\ sw sp, 8(t0)
|
||||
\\ sw gp, 12(t0)
|
||||
\\ sw tp, 16(t0)
|
||||
\\ sw t0, 20(t0)
|
||||
\\ sw t1, 24(t0)
|
||||
\\ sw t2, 28(t0)
|
||||
\\ sw s0, 32(t0)
|
||||
\\ sw s1, 36(t0)
|
||||
\\ sw a0, 40(t0)
|
||||
\\ sw a1, 44(t0)
|
||||
\\ sw a2, 48(t0)
|
||||
\\ sw a3, 52(t0)
|
||||
\\ sw a4, 56(t0)
|
||||
\\ sw a5, 60(t0)
|
||||
\\ sw a6, 64(t0)
|
||||
\\ sw a7, 68(t0)
|
||||
\\ sw s2, 72(t0)
|
||||
\\ sw s3, 76(t0)
|
||||
\\ sw s4, 80(t0)
|
||||
\\ sw s5, 84(t0)
|
||||
\\ sw s6, 88(t0)
|
||||
\\ sw s7, 92(t0)
|
||||
\\ sw s8, 96(t0)
|
||||
\\ sw s9, 100(t0)
|
||||
\\ sw s10, 104(t0)
|
||||
\\ sw s11, 108(t0)
|
||||
\\ sw t3, 112(t0)
|
||||
\\ sw t4, 116(t0)
|
||||
\\ sw t5, 120(t0)
|
||||
\\ sw t6, 124(t0)
|
||||
\\ jal ra, 1f
|
||||
\\1:
|
||||
\\ sw ra, 128(t0)
|
||||
\\ lw ra, 4(t0)
|
||||
:
|
||||
: [gprs] "{t0}" (&ctx),
|
||||
: .{ .memory = true });
|
||||
return ctx;
|
||||
}
|
||||
|
||||
pub fn dwarfRegisterBytes(ctx: *Riscv, register_num: u16) DwarfRegisterError![]u8 {
|
||||
switch (register_num) {
|
||||
0...31 => return @ptrCast(&ctx.r[register_num]),
|
||||
32 => return @ptrCast(&ctx.pc),
|
||||
|
||||
else => return error.InvalidRegister,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
const signal_ucontext_t = switch (native_os) {
|
||||
.linux => std.os.linux.ucontext_t,
|
||||
.emscripten => std.os.emscripten.ucontext_t,
|
||||
.freebsd => std.os.freebsd.ucontext_t,
|
||||
.macos, .ios, .tvos, .watchos, .visionos => extern struct {
|
||||
.driverkit, .macos, .ios, .tvos, .watchos, .visionos => extern struct {
|
||||
onstack: c_int,
|
||||
sigmask: std.c.sigset_t,
|
||||
stack: std.c.stack_t,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user