From b9360640cefd1aa30dedf71a0c6b7bddc51a6ae3 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Sun, 15 Apr 2018 18:12:00 -0400 Subject: [PATCH] add @atomicLoad builtin See #174 --- doc/langref.html.in | 21 +++++++- src/all_types.hpp | 11 ++++ src/codegen.cpp | 13 +++++ src/ir.cpp | 112 ++++++++++++++++++++++++++++++++++++++--- src/ir_print.cpp | 21 ++++++++ std/os/index.zig | 2 +- test/cases/atomics.zig | 14 +++++- 7 files changed, 183 insertions(+), 11 deletions(-) diff --git a/doc/langref.html.in b/doc/langref.html.in index d9436e55b7..5cbec218a9 100644 --- a/doc/langref.html.in +++ b/doc/langref.html.in @@ -3880,6 +3880,25 @@ pub fn main() void { {#header_open|@ArgType#}

TODO

{#header_close#} + {#header_open|@atomicLoad#} + 
@atomicLoad(comptime T: type, ptr: &const T, comptime ordering: builtin.AtomicOrder) -> T
+

+ This builtin function atomically dereferences a pointer and returns the value. +

+

+ T must be a pointer type, a bool, + or an integer whose bit count meets these requirements: +

+ +

+ TODO right now bool is not accepted. Also I think we could make non powers of 2 work fine, maybe + we can remove this restriction +

+ {#header_close#} {#header_open|@atomicRmw#} 
@atomicRmw(comptime T: type, ptr: &T, comptime op: builtin.AtomicRmwOp, operand: T, comptime ordering: builtin.AtomicOrder) -> T

@@ -6001,7 +6020,7 @@ hljs.registerLanguage("zig", function(t) { a = t.IR + "\\s*\\(", c = { keyword: "const align var extern stdcallcc nakedcc volatile export pub noalias inline struct packed enum union break return try catch test continue unreachable comptime and or asm defer errdefer if else switch while for fn use bool f32 f64 void type noreturn error i8 u8 i16 u16 i32 u32 i64 u64 isize usize i8w u8w i16w i32w u32w i64w u64w isizew usizew c_short c_ushort c_int c_uint c_long c_ulong c_longlong c_ulonglong", - built_in: "breakpoint returnAddress frameAddress fieldParentPtr setFloatMode IntType OpaqueType compileError compileLog setCold setRuntimeSafety setEvalBranchQuota offsetOf memcpy inlineCall setGlobalLinkage setGlobalSection divTrunc divFloor enumTagName intToPtr ptrToInt panic canImplicitCast ptrCast bitCast rem mod memset sizeOf alignOf alignCast maxValue minValue memberCount memberName memberType typeOf addWithOverflow subWithOverflow mulWithOverflow shlWithOverflow shlExact shrExact cInclude cDefine cUndef ctz clz import cImport errorName embedFile cmpxchg fence divExact truncate atomicRmw sqrt", + built_in: "atomicLoad breakpoint returnAddress frameAddress fieldParentPtr setFloatMode IntType OpaqueType compileError compileLog setCold setRuntimeSafety setEvalBranchQuota offsetOf memcpy inlineCall setGlobalLinkage setGlobalSection divTrunc divFloor enumTagName intToPtr ptrToInt panic canImplicitCast ptrCast bitCast rem mod memset sizeOf alignOf alignCast maxValue minValue memberCount memberName memberType typeOf addWithOverflow subWithOverflow mulWithOverflow shlWithOverflow shlExact shrExact cInclude cDefine cUndef ctz clz import cImport errorName embedFile cmpxchg fence divExact truncate atomicRmw sqrt", literal: "true false null undefined" }, n = [e, t.CLCM, t.CBCM, s, r]; diff --git a/src/all_types.hpp b/src/all_types.hpp index b43214a60e..708ad81791 100644 --- a/src/all_types.hpp +++ b/src/all_types.hpp @@ -1347,6 +1347,7 @@ enum BuiltinFnId { BuiltinFnIdExport, BuiltinFnIdErrorReturnTrace, BuiltinFnIdAtomicRmw, + BuiltinFnIdAtomicLoad, }; struct BuiltinFnEntry { @@ -2043,6 +2044,7 @@ enum IrInstructionId { IrInstructionIdCoroPromise, IrInstructionIdCoroAllocHelper, IrInstructionIdAtomicRmw, + IrInstructionIdAtomicLoad, IrInstructionIdPromiseResultType, IrInstructionIdAwaitBookkeeping, IrInstructionIdSaveErrRetAddr, @@ -3003,6 +3005,15 @@ struct IrInstructionAtomicRmw { AtomicOrder resolved_ordering; }; +struct IrInstructionAtomicLoad { + IrInstruction base; + + IrInstruction *operand_type; + IrInstruction *ptr; + IrInstruction *ordering; + AtomicOrder resolved_ordering; +}; + struct IrInstructionPromiseResultType { IrInstruction base; diff --git a/src/codegen.cpp b/src/codegen.cpp index 7a0117421a..9f319d9122 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -4385,6 +4385,16 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, IrExecutable *executable, return LLVMBuildIntToPtr(g->builder, uncasted_result, operand_type->type_ref, ""); } +static LLVMValueRef ir_render_atomic_load(CodeGen *g, IrExecutable *executable, + IrInstructionAtomicLoad *instruction) +{ + LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->resolved_ordering); + LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr); + LLVMValueRef load_inst = gen_load(g, ptr, instruction->ptr->value.type, ""); + LLVMSetOrdering(load_inst, ordering); + return load_inst; +} + static LLVMValueRef ir_render_merge_err_ret_traces(CodeGen *g, IrExecutable *executable, IrInstructionMergeErrRetTraces *instruction) { @@ -4628,6 +4638,8 @@ static LLVMValueRef ir_render_instruction(CodeGen *g, IrExecutable *executable, return ir_render_coro_alloc_helper(g, executable, (IrInstructionCoroAllocHelper *)instruction); case IrInstructionIdAtomicRmw: return ir_render_atomic_rmw(g, executable, (IrInstructionAtomicRmw *)instruction); + case IrInstructionIdAtomicLoad: + return ir_render_atomic_load(g, executable, (IrInstructionAtomicLoad *)instruction); case IrInstructionIdSaveErrRetAddr: return ir_render_save_err_ret_addr(g, executable, (IrInstructionSaveErrRetAddr *)instruction); case IrInstructionIdMergeErrRetTraces: @@ -6136,6 +6148,7 @@ static void define_builtin_fns(CodeGen *g) { create_builtin_fn(g, BuiltinFnIdExport, "export", 3); create_builtin_fn(g, BuiltinFnIdErrorReturnTrace, "errorReturnTrace", 0); create_builtin_fn(g, BuiltinFnIdAtomicRmw, "atomicRmw", 5); + create_builtin_fn(g, BuiltinFnIdAtomicLoad, "atomicLoad", 3); } static const char *bool_to_str(bool b) { diff --git a/src/ir.cpp b/src/ir.cpp index 08229b8bb3..d43efe0190 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -709,6 +709,10 @@ static constexpr IrInstructionId ir_instruction_id(IrInstructionAtomicRmw *) { return IrInstructionIdAtomicRmw; } +static constexpr IrInstructionId ir_instruction_id(IrInstructionAtomicLoad *) { + return IrInstructionIdAtomicLoad; +} + static constexpr IrInstructionId ir_instruction_id(IrInstructionPromiseResultType *) { return IrInstructionIdPromiseResultType; } @@ -2673,6 +2677,23 @@ static IrInstruction *ir_build_atomic_rmw(IrBuilder *irb, Scope *scope, AstNode return &instruction->base; } +static IrInstruction *ir_build_atomic_load(IrBuilder *irb, Scope *scope, AstNode *source_node, + IrInstruction *operand_type, IrInstruction *ptr, + IrInstruction *ordering, AtomicOrder resolved_ordering) +{ + IrInstructionAtomicLoad *instruction = ir_build_instruction(irb, scope, source_node); + instruction->operand_type = operand_type; + instruction->ptr = ptr; + instruction->ordering = ordering; + instruction->resolved_ordering = resolved_ordering; + + if (operand_type != nullptr) ir_ref_instruction(operand_type, irb->current_basic_block); + ir_ref_instruction(ptr, irb->current_basic_block); + if (ordering != nullptr) ir_ref_instruction(ordering, irb->current_basic_block); + + return &instruction->base; +} + static IrInstruction *ir_build_promise_result_type(IrBuilder *irb, Scope *scope, AstNode *source_node, IrInstruction *promise_type) { @@ -4303,6 +4324,27 @@ static IrInstruction *ir_gen_builtin_fn_call(IrBuilder *irb, Scope *scope, AstNo // these 2 values don't mean anything since we passed non-null values for other args AtomicRmwOp_xchg, AtomicOrderMonotonic); } + case BuiltinFnIdAtomicLoad: + { + AstNode *arg0_node = node->data.fn_call_expr.params.at(0); + IrInstruction *arg0_value = ir_gen_node(irb, arg0_node, scope); + if (arg0_value == irb->codegen->invalid_instruction) + return arg0_value; + + AstNode *arg1_node = node->data.fn_call_expr.params.at(1); + IrInstruction *arg1_value = ir_gen_node(irb, arg1_node, scope); + if (arg1_value == irb->codegen->invalid_instruction) + return arg1_value; + + AstNode *arg2_node = node->data.fn_call_expr.params.at(2); + IrInstruction *arg2_value = ir_gen_node(irb, arg2_node, scope); + if (arg2_value == irb->codegen->invalid_instruction) + return arg2_value; + + return ir_build_atomic_load(irb, scope, node, arg0_value, arg1_value, arg2_value, + // this value does not mean anything since we passed non-null values for other arg + AtomicOrderMonotonic); + } } zig_unreachable(); } @@ -17898,35 +17940,43 @@ static TypeTableEntry *ir_analyze_instruction_coro_alloc_helper(IrAnalyze *ira, return result->value.type; } -static TypeTableEntry *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstructionAtomicRmw *instruction) { - TypeTableEntry *operand_type = ir_resolve_type(ira, instruction->operand_type->other); - if (type_is_invalid(operand_type)) { +static TypeTableEntry *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstruction *op) { + TypeTableEntry *operand_type = ir_resolve_type(ira, op); + if (type_is_invalid(operand_type)) return ira->codegen->builtin_types.entry_invalid; - } + if (operand_type->id == TypeTableEntryIdInt) { if (operand_type->data.integral.bit_count < 8) { - ir_add_error(ira, &instruction->base, + ir_add_error(ira, op, buf_sprintf("expected integer type 8 bits or larger, found %" PRIu32 "-bit integer type", operand_type->data.integral.bit_count)); return ira->codegen->builtin_types.entry_invalid; } if (operand_type->data.integral.bit_count > ira->codegen->pointer_size_bytes * 8) { - ir_add_error(ira, &instruction->base, + ir_add_error(ira, op, buf_sprintf("expected integer type pointer size or smaller, found %" PRIu32 "-bit integer type", operand_type->data.integral.bit_count)); return ira->codegen->builtin_types.entry_invalid; } if (!is_power_of_2(operand_type->data.integral.bit_count)) { - ir_add_error(ira, &instruction->base, + ir_add_error(ira, op, buf_sprintf("%" PRIu32 "-bit integer type is not a power of 2", operand_type->data.integral.bit_count)); return ira->codegen->builtin_types.entry_invalid; } } else if (get_codegen_ptr_type(operand_type) == nullptr) { - ir_add_error(ira, &instruction->base, + ir_add_error(ira, op, buf_sprintf("expected integer or pointer type, found '%s'", buf_ptr(&operand_type->name))); return ira->codegen->builtin_types.entry_invalid; } + return operand_type; +} + +static TypeTableEntry *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstructionAtomicRmw *instruction) { + TypeTableEntry *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->other); + if (type_is_invalid(operand_type)) + return ira->codegen->builtin_types.entry_invalid; + IrInstruction *ptr_inst = instruction->ptr->other; if (type_is_invalid(ptr_inst->value.type)) return ira->codegen->builtin_types.entry_invalid; @@ -17974,6 +18024,49 @@ static TypeTableEntry *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstr return result->value.type; } +static TypeTableEntry *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstructionAtomicLoad *instruction) { + TypeTableEntry *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->other); + if (type_is_invalid(operand_type)) + return ira->codegen->builtin_types.entry_invalid; + + IrInstruction *ptr_inst = instruction->ptr->other; + if (type_is_invalid(ptr_inst->value.type)) + return ira->codegen->builtin_types.entry_invalid; + + TypeTableEntry *ptr_type = get_pointer_to_type(ira->codegen, operand_type, true); + IrInstruction *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); + if (type_is_invalid(casted_ptr->value.type)) + return ira->codegen->builtin_types.entry_invalid; + + AtomicOrder ordering; + if (instruction->ordering == nullptr) { + ordering = instruction->resolved_ordering; + } else { + if (!ir_resolve_atomic_order(ira, instruction->ordering->other, &ordering)) + return ira->codegen->builtin_types.entry_invalid; + } + + if (ordering == AtomicOrderRelease || ordering == AtomicOrderAcqRel) { + assert(instruction->ordering != nullptr); + ir_add_error(ira, instruction->ordering, + buf_sprintf("@atomicLoad atomic ordering must not be Release or AcqRel")); + return ira->codegen->builtin_types.entry_invalid; + } + + if (instr_is_comptime(casted_ptr)) { + IrInstruction *result = ir_get_deref(ira, &instruction->base, casted_ptr); + ir_link_new_instruction(result, &instruction->base); + assert(result->value.type != nullptr); + return result->value.type; + } + + IrInstruction *result = ir_build_atomic_load(&ira->new_irb, instruction->base.scope, + instruction->base.source_node, nullptr, casted_ptr, nullptr, ordering); + ir_link_new_instruction(result, &instruction->base); + result->value.type = operand_type; + return result->value.type; +} + static TypeTableEntry *ir_analyze_instruction_promise_result_type(IrAnalyze *ira, IrInstructionPromiseResultType *instruction) { TypeTableEntry *promise_type = ir_resolve_type(ira, instruction->promise_type->other); if (type_is_invalid(promise_type)) @@ -18357,6 +18450,8 @@ static TypeTableEntry *ir_analyze_instruction_nocast(IrAnalyze *ira, IrInstructi return ir_analyze_instruction_coro_alloc_helper(ira, (IrInstructionCoroAllocHelper *)instruction); case IrInstructionIdAtomicRmw: return ir_analyze_instruction_atomic_rmw(ira, (IrInstructionAtomicRmw *)instruction); + case IrInstructionIdAtomicLoad: + return ir_analyze_instruction_atomic_load(ira, (IrInstructionAtomicLoad *)instruction); case IrInstructionIdPromiseResultType: return ir_analyze_instruction_promise_result_type(ira, (IrInstructionPromiseResultType *)instruction); case IrInstructionIdAwaitBookkeeping: @@ -18584,6 +18679,7 @@ bool ir_has_side_effects(IrInstruction *instruction) { case IrInstructionIdCoroPromise: case IrInstructionIdPromiseResultType: case IrInstructionIdSqrt: + case IrInstructionIdAtomicLoad: return false; case IrInstructionIdAsm: diff --git a/src/ir_print.cpp b/src/ir_print.cpp index 5f8dd60187..45b666ae73 100644 --- a/src/ir_print.cpp +++ b/src/ir_print.cpp @@ -1172,6 +1172,24 @@ static void ir_print_atomic_rmw(IrPrint *irp, IrInstructionAtomicRmw *instructio fprintf(irp->f, ")"); } +static void ir_print_atomic_load(IrPrint *irp, IrInstructionAtomicLoad *instruction) { + fprintf(irp->f, "@atomicLoad("); + if (instruction->operand_type != nullptr) { + ir_print_other_instruction(irp, instruction->operand_type); + } else { + fprintf(irp->f, "[TODO print]"); + } + fprintf(irp->f, ","); + ir_print_other_instruction(irp, instruction->ptr); + fprintf(irp->f, ","); + if (instruction->ordering != nullptr) { + ir_print_other_instruction(irp, instruction->ordering); + } else { + fprintf(irp->f, "[TODO print]"); + } + fprintf(irp->f, ")"); +} + static void ir_print_await_bookkeeping(IrPrint *irp, IrInstructionAwaitBookkeeping *instruction) { fprintf(irp->f, "@awaitBookkeeping("); ir_print_other_instruction(irp, instruction->promise_result_type); @@ -1605,6 +1623,9 @@ static void ir_print_instruction(IrPrint *irp, IrInstruction *instruction) { case IrInstructionIdSqrt: ir_print_sqrt(irp, (IrInstructionSqrt *)instruction); break; + case IrInstructionIdAtomicLoad: + ir_print_atomic_load(irp, (IrInstructionAtomicLoad *)instruction); + break; } fprintf(irp->f, "\n"); } diff --git a/std/os/index.zig b/std/os/index.zig index 15b54f2e98..dbdb8c90cd 100644 --- a/std/os/index.zig +++ b/std/os/index.zig @@ -2392,7 +2392,7 @@ pub const Thread = struct { pub fn wait(self: &const Thread) void { while (true) { - const pid_value = self.pid; // TODO atomic load + const pid_value = @atomicLoad(i32, &self.pid, builtin.AtomicOrder.SeqCst); if (pid_value == 0) break; const rc = linux.futex_wait(@ptrToInt(&self.pid), linux.FUTEX_WAIT, pid_value, null); switch (linux.getErrno(rc)) { diff --git a/test/cases/atomics.zig b/test/cases/atomics.zig index e8e81b76e6..323906e4a4 100644 --- a/test/cases/atomics.zig +++ b/test/cases/atomics.zig @@ -15,13 +15,25 @@ test "fence" { x = 5678; } -test "atomicrmw" { +test "atomicrmw and atomicload" { var data: u8 = 200; testAtomicRmw(&data); assert(data == 42); + testAtomicLoad(&data); } fn testAtomicRmw(ptr: &u8) void { const prev_value = @atomicRmw(u8, ptr, AtomicRmwOp.Xchg, 42, AtomicOrder.SeqCst); assert(prev_value == 200); + comptime { + var x: i32 = 1234; + const y: i32 = 12345; + assert(@atomicLoad(i32, &x, AtomicOrder.SeqCst) == 1234); + assert(@atomicLoad(i32, &y, AtomicOrder.SeqCst) == 12345); + } +} + +fn testAtomicLoad(ptr: &u8) void { + const x = @atomicLoad(u8, ptr, AtomicOrder.SeqCst); + assert(x == 42); }