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Merge pull request #15727 from jacobly0/x86_64-behavior
x86_64: behavior
This commit is contained in:
Andrew Kelley
GitHub
commit
b873ce1e0e
File diff suppressed because it is too large
Load Diff
@ -178,7 +178,7 @@ pub fn format(
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try writer.print("+{s} ", .{tag});
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},
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.m, .mi, .m1, .mc, .vmi => try writer.print("/{d} ", .{encoding.modRmExt()}),
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.mr, .rm, .rmi, .mri, .mrc, .rvm, .rvmi, .mvr => try writer.writeAll("/r "),
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.mr, .rm, .rmi, .mri, .mrc, .rm0, .rvm, .rvmr, .rvmi, .mvr => try writer.writeAll("/r "),
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}
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switch (encoding.data.op_en) {
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@ -202,7 +202,8 @@ pub fn format(
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};
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try writer.print("{s} ", .{tag});
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},
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.np, .fd, .td, .o, .m, .m1, .mc, .mr, .rm, .mrc, .rvm, .mvr => {},
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.rvmr => try writer.writeAll("/is4 "),
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.np, .fd, .td, .o, .m, .m1, .mc, .mr, .rm, .mrc, .rm0, .rvm, .mvr => {},
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}
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try writer.print("{s} ", .{@tagName(encoding.mnemonic)});
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@ -262,6 +263,7 @@ pub const Mnemonic = enum {
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fisttp, fld,
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// MMX
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movd, movq,
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packssdw, packsswb, packuswb,
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paddb, paddd, paddq, paddsb, paddsw, paddusb, paddusw, paddw,
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pand, pandn, por, pxor,
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pmulhw, pmullw,
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@ -270,7 +272,7 @@ pub const Mnemonic = enum {
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addps, addss,
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andps,
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andnps,
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cmpss,
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cmpps, cmpss,
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cvtpi2ps, cvtps2pi, cvtsi2ss, cvtss2si, cvttps2pi, cvttss2si,
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divps, divss,
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maxps, maxss,
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@ -290,7 +292,7 @@ pub const Mnemonic = enum {
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addpd, addsd,
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andpd,
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andnpd,
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//cmpsd,
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cmppd, //cmpsd,
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cvtdq2pd, cvtdq2ps, cvtpd2dq, cvtpd2pi, cvtpd2ps, cvtpi2pd,
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cvtps2dq, cvtps2pd, cvtsd2si, cvtsd2ss, cvtsi2sd, cvtss2sd,
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cvttpd2dq, cvttpd2pi, cvttps2dq, cvttsd2si,
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@ -315,8 +317,10 @@ pub const Mnemonic = enum {
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// SSE3
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movddup, movshdup, movsldup,
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// SSE4.1
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blendpd, blendps, blendvpd, blendvps,
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extractps,
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insertps,
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packusdw,
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pextrb, pextrd, pextrq,
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pinsrb, pinsrd, pinsrq,
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pmaxsb, pmaxsd, pmaxud, pmaxuw, pminsb, pminsd, pminud, pminuw,
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@ -325,7 +329,9 @@ pub const Mnemonic = enum {
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// AVX
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vaddpd, vaddps, vaddsd, vaddss,
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vandnpd, vandnps, vandpd, vandps,
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vblendpd, vblendps, vblendvpd, vblendvps,
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vbroadcastf128, vbroadcastsd, vbroadcastss,
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vcmppd, vcmpps, vcmpsd, vcmpss,
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vcvtdq2pd, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps,
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vcvtps2dq, vcvtps2pd, vcvtsd2si, vcvtsd2ss,
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vcvtsi2sd, vcvtsi2ss, vcvtss2sd, vcvtss2si,
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@ -347,6 +353,7 @@ pub const Mnemonic = enum {
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vmovupd, vmovups,
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vmulpd, vmulps, vmulsd, vmulss,
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vorpd, vorps,
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vpackssdw, vpacksswb, vpackusdw, vpackuswb,
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vpaddb, vpaddd, vpaddq, vpaddsb, vpaddsw, vpaddusb, vpaddusw, vpaddw,
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vpand, vpandn,
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vpextrb, vpextrd, vpextrq, vpextrw,
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@ -385,7 +392,7 @@ pub const OpEn = enum {
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fd, td,
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m1, mc, mi, mr, rm,
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rmi, mri, mrc,
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vmi, rvm, rvmi, mvr,
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rm0, vmi, rvm, rvmr, rvmi, mvr,
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// zig fmt: on
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};
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@ -407,7 +414,7 @@ pub const Op = enum {
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moffs,
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sreg,
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st, mm, mm_m64,
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xmm, xmm_m32, xmm_m64, xmm_m128,
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xmm0, xmm, xmm_m32, xmm_m64, xmm_m128,
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ymm, ymm_m256,
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// zig fmt: on
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@ -436,7 +443,9 @@ pub const Op = enum {
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.segment => .sreg,
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.x87 => .st,
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.mmx => .mm,
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.sse => switch (reg.bitSize()) {
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.sse => if (reg == .xmm0)
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.xmm0
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else switch (reg.bitSize()) {
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128 => .xmm,
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256 => .ymm,
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else => unreachable,
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@ -494,7 +503,7 @@ pub const Op = enum {
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.eax, .r32, .rm32, .r32_m16 => unreachable,
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.rax, .r64, .rm64, .r64_m16 => unreachable,
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.st, .mm, .mm_m64 => unreachable,
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.xmm, .xmm_m32, .xmm_m64, .xmm_m128 => unreachable,
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.xmm0, .xmm, .xmm_m32, .xmm_m64, .xmm_m128 => unreachable,
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.ymm, .ymm_m256 => unreachable,
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.m8, .m16, .m32, .m64, .m80, .m128, .m256 => unreachable,
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.unity => 1,
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@ -516,7 +525,7 @@ pub const Op = enum {
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.eax, .r32, .rm32, .r32_m8, .r32_m16 => 32,
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.rax, .r64, .rm64, .r64_m16, .mm, .mm_m64 => 64,
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.st => 80,
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.xmm, .xmm_m32, .xmm_m64, .xmm_m128 => 128,
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.xmm0, .xmm, .xmm_m32, .xmm_m64, .xmm_m128 => 128,
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.ymm, .ymm_m256 => 256,
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};
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}
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@ -526,7 +535,8 @@ pub const Op = enum {
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.none, .o16, .o32, .o64, .moffs, .m, .sreg => unreachable,
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.unity, .imm8, .imm8s, .imm16, .imm16s, .imm32, .imm32s, .imm64 => unreachable,
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.rel8, .rel16, .rel32 => unreachable,
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.al, .cl, .r8, .ax, .r16, .eax, .r32, .rax, .r64, .st, .mm, .xmm, .ymm => unreachable,
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.al, .cl, .r8, .ax, .r16, .eax, .r32, .rax, .r64 => unreachable,
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.st, .mm, .xmm0, .xmm, .ymm => unreachable,
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.m8, .rm8, .r32_m8 => 8,
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.m16, .rm16, .r32_m16, .r64_m16 => 16,
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.m32, .rm32, .xmm_m32 => 32,
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@ -558,7 +568,7 @@ pub const Op = enum {
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.rm8, .rm16, .rm32, .rm64,
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.r32_m8, .r32_m16, .r64_m16,
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.st, .mm, .mm_m64,
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.xmm, .xmm_m32, .xmm_m64, .xmm_m128,
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.xmm0, .xmm, .xmm_m32, .xmm_m64, .xmm_m128,
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.ymm, .ymm_m256,
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=> true,
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else => false,
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@ -612,7 +622,7 @@ pub const Op = enum {
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.sreg => .segment,
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.st => .x87,
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.mm, .mm_m64 => .mmx,
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.xmm, .xmm_m32, .xmm_m64, .xmm_m128 => .sse,
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.xmm0, .xmm, .xmm_m32, .xmm_m64, .xmm_m128 => .sse,
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.ymm, .ymm_m256 => .sse,
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};
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}
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@ -629,7 +639,7 @@ pub const Op = enum {
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else => {
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if (op.isRegister() and target.isRegister()) {
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return switch (target) {
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.cl, .al, .ax, .eax, .rax => op == target,
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.cl, .al, .ax, .eax, .rax, .xmm0 => op == target,
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else => op.class() == target.class() and op.regBitSize() == target.regBitSize(),
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};
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}
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@ -377,6 +377,7 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void {
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.r => inst.data.r.fixes,
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.rr => inst.data.rr.fixes,
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.rrr => inst.data.rrr.fixes,
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.rrrr => inst.data.rrrr.fixes,
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.rrri => inst.data.rrri.fixes,
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.rri_s, .rri_u => inst.data.rri.fixes,
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.ri_s, .ri_u => inst.data.ri.fixes,
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@ -430,6 +431,12 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void {
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.{ .reg = inst.data.rrr.r2 },
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.{ .reg = inst.data.rrr.r3 },
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},
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.rrrr => &.{
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.{ .reg = inst.data.rrrr.r1 },
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.{ .reg = inst.data.rrrr.r2 },
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.{ .reg = inst.data.rrrr.r3 },
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.{ .reg = inst.data.rrrr.r4 },
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},
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.rrri => &.{
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.{ .reg = inst.data.rrri.r1 },
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.{ .reg = inst.data.rrri.r2 },
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@ -446,6 +446,12 @@ pub const Inst = struct {
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/// Bitwise logical xor of packed double-precision floating-point values
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xor,
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/// Pack with signed saturation
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ackssw,
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/// Pack with signed saturation
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ackssd,
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/// Pack with unsigned saturation
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ackusw,
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/// Add packed signed integers with signed saturation
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adds,
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/// Add packed unsigned integers with unsigned saturation
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@ -596,6 +602,18 @@ pub const Inst = struct {
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/// Replicate single floating-point values
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movsldup,
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/// Pack with unsigned saturation
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ackusd,
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/// Blend packed single-precision floating-point values
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/// Blend scalar single-precision floating-point values
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/// Blend packed double-precision floating-point values
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/// Blend scalar double-precision floating-point values
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blend,
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/// Variable blend packed single-precision floating-point values
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/// Variable blend scalar single-precision floating-point values
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/// Variable blend packed double-precision floating-point values
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/// Variable blend scalar double-precision floating-point values
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blendv,
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/// Extract packed floating-point values
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extract,
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/// Insert scalar single-precision floating-point value
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@ -651,6 +669,9 @@ pub const Inst = struct {
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/// Register, register, register operands.
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/// Uses `rrr` payload.
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rrr,
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/// Register, register, register, register operands.
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/// Uses `rrrr` payload.
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rrrr,
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/// Register, register, register, immediate (byte) operands.
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/// Uses `rrri` payload.
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rrri,
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@ -870,6 +891,13 @@ pub const Inst = struct {
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r2: Register,
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r3: Register,
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},
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rrrr: struct {
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fixes: Fixes = ._,
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r1: Register,
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r2: Register,
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r3: Register,
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r4: Register,
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},
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rrri: struct {
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fixes: Fixes = ._,
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r1: Register,
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@ -226,8 +226,8 @@ pub const Instruction = struct {
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else => {
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const mem_op = switch (data.op_en) {
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.m, .mi, .m1, .mc, .mr, .mri, .mrc, .mvr => inst.ops[0],
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.rm, .rmi, .vmi => inst.ops[1],
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.rvm, .rvmi => inst.ops[2],
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.rm, .rmi, .rm0, .vmi => inst.ops[1],
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.rvm, .rvmr, .rvmi => inst.ops[2],
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else => unreachable,
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};
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switch (mem_op) {
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@ -235,7 +235,7 @@ pub const Instruction = struct {
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const rm = switch (data.op_en) {
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.m, .mi, .m1, .mc, .vmi => enc.modRmExt(),
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.mr, .mri, .mrc => inst.ops[1].reg.lowEnc(),
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.rm, .rmi, .rvm, .rvmi => inst.ops[0].reg.lowEnc(),
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.rm, .rmi, .rm0, .rvm, .rvmr, .rvmi => inst.ops[0].reg.lowEnc(),
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.mvr => inst.ops[2].reg.lowEnc(),
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else => unreachable,
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};
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@ -245,7 +245,7 @@ pub const Instruction = struct {
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const op = switch (data.op_en) {
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.m, .mi, .m1, .mc, .vmi => .none,
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.mr, .mri, .mrc => inst.ops[1],
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.rm, .rmi, .rvm, .rvmi => inst.ops[0],
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.rm, .rmi, .rm0, .rvm, .rvmr, .rvmi => inst.ops[0],
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.mvr => inst.ops[2],
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else => unreachable,
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};
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@ -257,6 +257,7 @@ pub const Instruction = struct {
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switch (data.op_en) {
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.mi => try encodeImm(inst.ops[1].imm, data.ops[1], encoder),
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.rmi, .mri, .vmi => try encodeImm(inst.ops[2].imm, data.ops[2], encoder),
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.rvmr => try encoder.imm8(@as(u8, inst.ops[3].reg.enc()) << 4),
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.rvmi => try encodeImm(inst.ops[3].imm, data.ops[3], encoder),
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else => {},
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}
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@ -298,7 +299,7 @@ pub const Instruction = struct {
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.i, .zi, .o, .oi, .d, .np => null,
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.fd => inst.ops[1].mem.base().reg,
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.td => inst.ops[0].mem.base().reg,
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.rm, .rmi => if (inst.ops[1].isSegmentRegister())
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.rm, .rmi, .rm0 => if (inst.ops[1].isSegmentRegister())
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switch (inst.ops[1]) {
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.reg => |reg| reg,
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.mem => |mem| mem.base().reg,
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@ -314,7 +315,7 @@ pub const Instruction = struct {
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}
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else
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null,
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.vmi, .rvm, .rvmi, .mvr => unreachable,
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.vmi, .rvm, .rvmr, .rvmi, .mvr => unreachable,
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};
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if (segment_override) |seg| {
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legacy.setSegmentOverride(seg);
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@ -333,23 +334,23 @@ pub const Instruction = struct {
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switch (op_en) {
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.np, .i, .zi, .fd, .td, .d => {},
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.o, .oi => rex.b = inst.ops[0].reg.isExtended(),
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.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc => {
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.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc, .rm0 => {
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const r_op = switch (op_en) {
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.rm, .rmi => inst.ops[0],
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.rm, .rmi, .rm0 => inst.ops[0],
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.mr, .mri, .mrc => inst.ops[1],
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else => .none,
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};
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rex.r = r_op.isBaseExtended();
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const b_x_op = switch (op_en) {
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.rm, .rmi => inst.ops[1],
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.rm, .rmi, .rm0 => inst.ops[1],
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.m, .mi, .m1, .mc, .mr, .mri, .mrc => inst.ops[0],
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else => unreachable,
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};
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rex.b = b_x_op.isBaseExtended();
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rex.x = b_x_op.isIndexExtended();
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},
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.vmi, .rvm, .rvmi, .mvr => unreachable,
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.vmi, .rvm, .rvmr, .rvmi, .mvr => unreachable,
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}
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try encoder.rex(rex);
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@ -367,9 +368,9 @@ pub const Instruction = struct {
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switch (op_en) {
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.np, .i, .zi, .fd, .td, .d => {},
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.o, .oi => vex.b = inst.ops[0].reg.isExtended(),
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.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc, .vmi, .rvm, .rvmi, .mvr => {
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.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc, .rm0, .vmi, .rvm, .rvmr, .rvmi, .mvr => {
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const r_op = switch (op_en) {
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.rm, .rmi, .rvm, .rvmi => inst.ops[0],
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.rm, .rmi, .rm0, .rvm, .rvmr, .rvmi => inst.ops[0],
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.mr, .mri, .mrc => inst.ops[1],
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.mvr => inst.ops[2],
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.m, .mi, .m1, .mc, .vmi => .none,
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@ -378,9 +379,9 @@ pub const Instruction = struct {
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vex.r = r_op.isBaseExtended();
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const b_x_op = switch (op_en) {
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.rm, .rmi, .vmi => inst.ops[1],
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.rm, .rmi, .rm0, .vmi => inst.ops[1],
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.m, .mi, .m1, .mc, .mr, .mri, .mrc, .mvr => inst.ops[0],
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.rvm, .rvmi => inst.ops[2],
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.rvm, .rvmr, .rvmi => inst.ops[2],
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else => unreachable,
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};
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vex.b = b_x_op.isBaseExtended();
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@ -408,7 +409,7 @@ pub const Instruction = struct {
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switch (op_en) {
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else => {},
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.vmi => vex.v = inst.ops[0].reg,
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.rvm, .rvmi => vex.v = inst.ops[1].reg,
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.rvm, .rvmr, .rvmi => vex.v = inst.ops[1].reg,
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}
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try encoder.vex(vex);
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@ -846,6 +846,8 @@ pub const table = [_]Entry{
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.{ .andps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x54 }, 0, .none, .sse },
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.{ .cmpps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x0f, 0xc2 }, 0, .none, .sse },
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.{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .none, .sse },
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||||
|
||||
.{ .cvtpi2ps, .rm, &.{ .xmm, .mm_m64 }, &.{ 0x0f, 0x2a }, 0, .none, .sse },
|
||||
@ -917,6 +919,8 @@ pub const table = [_]Entry{
|
||||
|
||||
.{ .andpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x54 }, 0, .none, .sse2 },
|
||||
|
||||
.{ .cmppd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc2 }, 0, .none, .sse2 },
|
||||
|
||||
.{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .none, .sse2 },
|
||||
|
||||
.{ .cvtdq2pd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0xe6 }, 0, .none, .sse2 },
|
||||
@ -992,6 +996,11 @@ pub const table = [_]Entry{
|
||||
|
||||
.{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },
|
||||
|
||||
.{ .packsswb, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x63 }, 0, .none, .sse2 },
|
||||
.{ .packssdw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6b }, 0, .none, .sse2 },
|
||||
|
||||
.{ .packuswb, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x67 }, 0, .none, .sse2 },
|
||||
|
||||
.{ .paddb, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfc }, 0, .none, .sse2 },
|
||||
.{ .paddw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfd }, 0, .none, .sse2 },
|
||||
.{ .paddd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfe }, 0, .none, .sse2 },
|
||||
@ -1085,10 +1094,20 @@ pub const table = [_]Entry{
|
||||
.{ .movsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .none, .sse3 },
|
||||
|
||||
// SSE4.1
|
||||
.{ .blendpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0d }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .blendps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0c }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .blendvpd, .rm0, &.{ .xmm, .xmm_m128, .xmm0 }, &.{ 0x66, 0x0f, 0x38, 0x15 }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .blendvps, .rm0, &.{ .xmm, .xmm_m128, .xmm0 }, &.{ 0x66, 0x0f, 0x38, 0x14 }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .extractps, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x17 }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .insertps, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x21 }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .packusdw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x2b }, 0, .none, .sse4_1 },
|
||||
|
||||
.{ .pextrb, .mri, &.{ .r32_m8, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x14 }, 0, .none, .sse4_1 },
|
||||
.{ .pextrd, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .none, .sse4_1 },
|
||||
.{ .pextrq, .mri, &.{ .rm64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .long, .sse4_1 },
|
||||
@ -1146,11 +1165,33 @@ pub const table = [_]Entry{
|
||||
.{ .vandps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x54 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vandps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x54 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vblendpd, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0d }, 0, .vex_128_wig, .avx },
|
||||
.{ .vblendpd, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0d }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vblendps, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0c }, 0, .vex_128_wig, .avx },
|
||||
.{ .vblendps, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0c }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vblendvpd, .rvmr, &.{ .xmm, .xmm, .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x3a, 0x4b }, 0, .vex_128_w0, .avx },
|
||||
.{ .vblendvpd, .rvmr, &.{ .ymm, .ymm, .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x3a, 0x4b }, 0, .vex_256_w0, .avx },
|
||||
|
||||
.{ .vblendvps, .rvmr, &.{ .xmm, .xmm, .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x3a, 0x4a }, 0, .vex_128_w0, .avx },
|
||||
.{ .vblendvps, .rvmr, &.{ .ymm, .ymm, .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x3a, 0x4a }, 0, .vex_256_w0, .avx },
|
||||
|
||||
.{ .vbroadcastss, .rm, &.{ .xmm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx },
|
||||
.{ .vbroadcastss, .rm, &.{ .ymm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx },
|
||||
.{ .vbroadcastsd, .rm, &.{ .ymm, .m64 }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx },
|
||||
.{ .vbroadcastf128, .rm, &.{ .ymm, .m128 }, &.{ 0x66, 0x0f, 0x38, 0x1a }, 0, .vex_256_w0, .avx },
|
||||
|
||||
.{ .vcmppd, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc2 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vcmppd, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0xc2 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vcmpps, .rvmi, &.{ .xmm, .xmm, .xmm_m128, .imm8 }, &.{ 0x0f, 0xc2 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vcmpps, .rvmi, &.{ .ymm, .ymm, .ymm_m256, .imm8 }, &.{ 0x0f, 0xc2 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vcmpsd, .rvmi, &.{ .xmm, .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .vex_lig_wig, .avx },
|
||||
|
||||
.{ .vcmpss, .rvmi, &.{ .xmm, .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .vex_lig_wig, .avx },
|
||||
|
||||
.{ .vcvtdq2pd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0xe6 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vcvtdq2pd, .rm, &.{ .ymm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0xe6 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
@ -1312,6 +1353,13 @@ pub const table = [_]Entry{
|
||||
.{ .vorps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x56 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vorps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x56 }, 0, .vex_256_wig, .avx },
|
||||
|
||||
.{ .vpacksswb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x63 }, 0, .vex_128_wig, .avx },
|
||||
.{ .vpackssdw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6b }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vpackusdw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x2b }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vpackuswb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x67 }, 0, .vex_128_wig, .avx },
|
||||
|
||||
.{ .vpaddb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfc }, 0, .vex_128_wig, .avx },
|
||||
.{ .vpaddw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfd }, 0, .vex_128_wig, .avx },
|
||||
.{ .vpaddd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xfe }, 0, .vex_128_wig, .avx },
|
||||
@ -1474,6 +1522,13 @@ pub const table = [_]Entry{
|
||||
.{ .vbroadcastss, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx2 },
|
||||
.{ .vbroadcastsd, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx2 },
|
||||
|
||||
.{ .vpacksswb, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x63 }, 0, .vex_256_wig, .avx2 },
|
||||
.{ .vpackssdw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6b }, 0, .vex_256_wig, .avx2 },
|
||||
|
||||
.{ .vpackusdw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x2b }, 0, .vex_256_wig, .avx2 },
|
||||
|
||||
.{ .vpackuswb, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x67 }, 0, .vex_256_wig, .avx2 },
|
||||
|
||||
.{ .vpaddb, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xfc }, 0, .vex_256_wig, .avx2 },
|
||||
.{ .vpaddw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xfd }, 0, .vex_256_wig, .avx2 },
|
||||
.{ .vpaddd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xfe }, 0, .vex_256_wig, .avx2 },
|
||||
|
||||
@ -747,15 +747,23 @@ pub fn generateSymbol(
|
||||
.Vector => switch (typed_value.val.tag()) {
|
||||
.bytes => {
|
||||
const bytes = typed_value.val.castTag(.bytes).?.data;
|
||||
const len = @intCast(usize, typed_value.ty.arrayLen());
|
||||
try code.ensureUnusedCapacity(len);
|
||||
const len = math.cast(usize, typed_value.ty.arrayLen()) orelse return error.Overflow;
|
||||
const padding = math.cast(usize, typed_value.ty.abiSize(target) - len) orelse
|
||||
return error.Overflow;
|
||||
try code.ensureUnusedCapacity(len + padding);
|
||||
code.appendSliceAssumeCapacity(bytes[0..len]);
|
||||
if (padding > 0) try code.writer().writeByteNTimes(0, padding);
|
||||
return Result.ok;
|
||||
},
|
||||
.aggregate => {
|
||||
const elem_vals = typed_value.val.castTag(.aggregate).?.data;
|
||||
const elem_ty = typed_value.ty.elemType();
|
||||
const len = @intCast(usize, typed_value.ty.arrayLen());
|
||||
const len = math.cast(usize, typed_value.ty.arrayLen()) orelse return error.Overflow;
|
||||
const padding = math.cast(usize, typed_value.ty.abiSize(target) -
|
||||
(math.divCeil(u64, elem_ty.bitSize(target) * len, 8) catch |err| switch (err) {
|
||||
error.DivisionByZero => unreachable,
|
||||
else => |e| return e,
|
||||
})) orelse return error.Overflow;
|
||||
for (elem_vals[0..len]) |elem_val| {
|
||||
switch (try generateSymbol(bin_file, src_loc, .{
|
||||
.ty = elem_ty,
|
||||
@ -765,13 +773,18 @@ pub fn generateSymbol(
|
||||
.fail => |em| return Result{ .fail = em },
|
||||
}
|
||||
}
|
||||
if (padding > 0) try code.writer().writeByteNTimes(0, padding);
|
||||
return Result.ok;
|
||||
},
|
||||
.repeated => {
|
||||
const array = typed_value.val.castTag(.repeated).?.data;
|
||||
const elem_ty = typed_value.ty.childType();
|
||||
const len = typed_value.ty.arrayLen();
|
||||
|
||||
const padding = math.cast(usize, typed_value.ty.abiSize(target) -
|
||||
(math.divCeil(u64, elem_ty.bitSize(target) * len, 8) catch |err| switch (err) {
|
||||
error.DivisionByZero => unreachable,
|
||||
else => |e| return e,
|
||||
})) orelse return error.Overflow;
|
||||
var index: u64 = 0;
|
||||
while (index < len) : (index += 1) {
|
||||
switch (try generateSymbol(bin_file, src_loc, .{
|
||||
@ -782,13 +795,17 @@ pub fn generateSymbol(
|
||||
.fail => |em| return Result{ .fail = em },
|
||||
}
|
||||
}
|
||||
if (padding > 0) try code.writer().writeByteNTimes(0, padding);
|
||||
return Result.ok;
|
||||
},
|
||||
.str_lit => {
|
||||
const str_lit = typed_value.val.castTag(.str_lit).?.data;
|
||||
const bytes = mod.string_literal_bytes.items[str_lit.index..][0..str_lit.len];
|
||||
try code.ensureUnusedCapacity(str_lit.len);
|
||||
const padding = math.cast(usize, typed_value.ty.abiSize(target) - str_lit.len) orelse
|
||||
return error.Overflow;
|
||||
try code.ensureUnusedCapacity(str_lit.len + padding);
|
||||
code.appendSliceAssumeCapacity(bytes);
|
||||
if (padding > 0) try code.writer().writeByteNTimes(0, padding);
|
||||
return Result.ok;
|
||||
},
|
||||
else => unreachable,
|
||||
|
||||
@ -35,7 +35,6 @@ test "@bitCast iX -> uX (8, 16, 128)" {
|
||||
|
||||
test "@bitCast iX -> uX exotic integers" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -82,7 +81,6 @@ fn conv_uN(comptime N: usize, x: std.meta.Int(.unsigned, N)) std.meta.Int(.signe
|
||||
|
||||
test "bitcast uX to bytes" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -14,7 +14,6 @@ fn foo(val: U) !void {
|
||||
test "runtime union init, most-aligned field != largest" {
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
|
||||
@ -816,7 +816,6 @@ test "array concatenation peer resolves element types - pointer" {
|
||||
|
||||
test "array concatenation sets the sentinel - value" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -855,7 +854,6 @@ test "array concatenation sets the sentinel - pointer" {
|
||||
|
||||
test "array multiplication sets the sentinel - value" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -1145,7 +1145,6 @@ test "nan negation f64" {
|
||||
|
||||
test "nan negation f128" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -783,7 +783,6 @@ test "basic @mulWithOverflow" {
|
||||
test "extensive @mulWithOverflow" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
|
||||
{
|
||||
@ -1055,7 +1054,6 @@ test "@subWithOverflow" {
|
||||
test "@shlWithOverflow" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
|
||||
{
|
||||
|
||||
@ -24,7 +24,8 @@ test "@max" {
|
||||
|
||||
test "@max on vectors" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64 and
|
||||
!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -72,7 +73,8 @@ test "@min" {
|
||||
|
||||
test "@min for vectors" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64 and
|
||||
!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -5,7 +5,6 @@ const maxInt = std.math.maxInt;
|
||||
const expect = std.testing.expect;
|
||||
|
||||
test "saturating add" {
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -79,7 +78,6 @@ test "saturating add 128bit" {
|
||||
}
|
||||
|
||||
test "saturating subtraction" {
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -61,7 +61,6 @@ test "truncate on comptime integer" {
|
||||
|
||||
test "truncate on vectors" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -1142,7 +1142,6 @@ test "loading the second vector from a slice of vectors" {
|
||||
|
||||
test "array of vectors is copied" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -5,7 +5,6 @@ const builtin = @import("builtin");
|
||||
const has_f80_rt = @import("builtin").cpu.arch == .x86_64;
|
||||
|
||||
test "integer widening" {
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user