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x86_64: implement @mulAdd of floats for baseline

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This commit is contained in:
Jacob Young 2023-10-08 04:04:04 -04:00
parent 35c9b717f7
commit b5dedd7c00
2 changed files with 147 additions and 124 deletions
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29
src/arch/x86_64/CodeGen.zig
View File

@ -12721,9 +12721,30 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {
const extra = self.air.extraData(Air.Bin, pl_op.payload).data;
const ty = self.typeOfIndex(inst);
if (!self.hasFeature(.fma)) return self.fail("TODO implement airMulAdd for {}", .{ty.fmt(mod)});
const ops = [3]Air.Inst.Ref{ extra.lhs, extra.rhs, pl_op.operand };
const result = result: {
if (switch (ty.scalarType(mod).floatBits(self.target.*)) {
16, 80, 128 => true,
32, 64 => !self.hasFeature(.fma),
else => unreachable,
}) {
if (ty.zigTypeTag(mod) != .Float) return self.fail("TODO implement airMulAdd for {}", .{
ty.fmt(mod),
});
var callee: ["__fma?".len]u8 = undefined;
break :result try self.genCall(.{ .lib = .{
.return_type = ty.toIntern(),
.param_types = &.{ ty.toIntern(), ty.toIntern(), ty.toIntern() },
.callee = std.fmt.bufPrint(&callee, "{s}fma{s}", .{
floatLibcAbiPrefix(ty),
floatLibcAbiSuffix(ty),
}) catch unreachable,
} }, &.{ ty, ty, ty }, &.{
.{ .air_ref = extra.lhs }, .{ .air_ref = extra.rhs }, .{ .air_ref = pl_op.operand },
});
}
var mcvs: [3]MCValue = undefined;
var locks = [1]?RegisterManager.RegisterLock{null} ** 3;
defer for (locks) |reg_lock| if (reg_lock) |lock| self.register_manager.unlockReg(lock);
@ -12856,7 +12877,9 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {
mop2_reg,
mops[2].mem(Memory.PtrSize.fromSize(abi_size)),
);
return self.finishAir(inst, mops[0], ops);
break :result mops[0];
};
return self.finishAir(inst, result, ops);
}
fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {

6
test/behavior/muladd.zig
View File

@ -32,11 +32,11 @@ fn testMulAdd() !void {
}
test "@mulAdd f16" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
try comptime testMulAdd16();
try testMulAdd16();
@ -50,12 +50,12 @@ fn testMulAdd16() !void {
}
test "@mulAdd f80" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_c and comptime builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
try comptime testMulAdd80();
try testMulAdd80();
@ -69,12 +69,12 @@ fn testMulAdd80() !void {
}
test "@mulAdd f128" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_c and comptime builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
try comptime testMulAdd128();
try testMulAdd128();