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x86_64: fix tlv references

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This commit is contained in:
Jacob Young 2023-04-25 21:43:49 -04:00
parent eff0e6a726
commit b5b0b55582
2 changed files with 6 additions and 2 deletions
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4
src/arch/x86_64/CodeGen.zig
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@ -7339,7 +7339,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
const atom_index = try self.getSymbolIndexForDecl(self.mod_fn.owner_decl);
if (self.bin_file.cast(link.File.MachO)) |_| {
_ = try self.addInst(.{
.tag = .mov_linker,
.tag = .lea_linker,
.ops = .tlv_reloc,
.data = .{ .payload = try self.addExtra(Mir.LeaRegisterReloc{
.reg = @enumToInt(Register.rdi),
@ -8609,7 +8609,7 @@ fn genTypedValue(self: *Self, arg_tv: TypedValue) InnerError!MCValue {
.memory => |addr| .{ .memory = addr },
.load_direct => |sym_index| .{ .load_direct = sym_index },
.load_got => |sym_index| .{ .lea_got = sym_index },
.load_tlv => |sym_index| .{ .load_tlv = sym_index },
.load_tlv => |sym_index| .{ .lea_tlv = sym_index },
},
.fail => |msg| {
self.err_msg = msg;

4
test/behavior/bugs/1851.zig
View File

@ -16,6 +16,10 @@ test "allocation and looping over 3-byte integer" {
return error.SkipZigTest; // TODO
}
if (builtin.zig_backend == .stage2_x86_64 and builtin.os.tag == .macos) {
return error.SkipZigTest; // TODO
}
try expect(@sizeOf(u24) == 4);
try expect(@sizeOf([1]u24) == 4);
try expect(@alignOf(u24) == 4);